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datasheet portable consumer device low-power, high-fidelity class-d amplifier acs32201 idt confidential 1 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 the acs32201 is a low-power, high-fidelity class-d ampli- fier targeted at portable applications such as tablet com- puters, personal navigation devices, portable projectors and speaker docks. built-in audio processing and a ddx tm class-d digital speaker amp lifier provide high fidel- ity audio for portable systems with enriched ?audio pres- ence?. target applications ? tablet computers ? portable navigation devices ? personal media players ? portable projectors ? speaker docks features ? filterless stereo ddx tm class d speaker driver ? 1w/channel (8 ) or 2w/channel (4 ), 0.05% thd+n typical ? tri-state ddx tm class d achieves low emi and high efficiency ? >80% efficiency at 1w ? spread spectrum support for reduced emi output power mode ? anti-pop circuitry ? built in audio controls and processing ? 3d stereo enhancement ? dual (cascaded) stereo 6-ba nd parametric equalizers ? programmable compressor/limiter/expander ? psychoacoustic bass and treble enhancement processing ?i2s data interface ? low power with built in power management ? very low standby and no-signal power consumption ? 1.8v digital / 1.7v analog supply for low power ? 2-wire (i 2 c compatible) control interface ? package options ? 68-pin dual row 6x6 mm tla package ? 36-pin single row 5x5 mm hla package preliminary ddx tm and the ddx logo are trademarks of apogee technology.
idt confidential 2 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier table of contents 1. overview ................................................................................................................... ............. 2 1.1. block diagrams ........................................................................................................... .......................2 1.2. audio outputs ............................................................................................................ ........................2 2. power management .......................................................................................................... 3 2.1. control registers ........................................................................................................ .......................3 2.2. stopping the master clock ................................................................................................ .................3 3. output audio processing ............................................................................................... 4 3.1. dc removal ............................................................................................................... .......................4 3.2. volume control ........................................................................................................... .......................5 3.3. digital dac volume control ............................................................................................... ................6 3.4. parametric equalizer ..................................................................................................... ....................6 3.4.1. prescaler & equalizer filter ................... ........................................................................ ......6 3.4.2. eq registers ........................................................................................................... .............7 3.4.3. equalizer, bass, treble c oefficient & equalizer prescaler ra m .........................................9 3.5. gain and dynamic range control ........................................................................................... ........12 3.6. limiter .................................................................................................................. ............................12 3.7. compressor ............................................................................................................... ......................13 3.7.1. configuration .......................................................................................................... ............14 3.7.2. controlling parameters ................................................................................................. ......14 3.7.3. overview ............................................................................................................... .............15 3.7.4. limiter/compressor registers ..................... ...................................................................... .17 3.7.5. expander registers ..................................................................................................... ......19 3.8. output effects ........................................................................................................... .......................20 3.9. stereo depth (3-d) enhancement ........................................................................................... ........20 3.10. psychoacoustic bass enhancement ..................... .................................................................... .....21 3.10.1. non-linear function ................................................................................................... ........21 3.10.2. signal processing summary ............................................................................................. 22 3.10.3. control points ........................................................................................................ ..........22 3.11. treble enhancement ...................................................................................................... ...............23 3.11.1. enhanced treble nlf ................................................................................................... ...23 3.11.2. signal processing summary ............................................................................................. 23 3.11.3. control points ........................................................................................................ ..........24 3.12. mute and de-emphasis .................................................................................................... .............24 3.13. mono operation and phase inversion ...................................................................................... .....24 3.13.1. dac control register ................................................................................................. ....24 3.14. analog outputs .......................................................................................................... ....................25 3.14.1. speaker outputs ....................................................................................................... .......25 3.14.2. class d audio processing ........................ ...................................................................... .25 3.15. other output capabilities ...... .............. .............. .............. .............. ........... ........... ........... ...............31 3.15.1. audio output control .................................................................................................. .....31 3.15.2. speaker enable ........................................................................................................ .......31 3.15.3. speaker operation ..................................................................................................... ......32 3.16. thermal shutdown ........................................................................................................ .................32 3.16.1. algorithm description: ................................................................................................ ......32 3.16.2. thermal trip points. .................................................................................................. .......33 3.16.3. temperature limit state diagram: ...................................................................................34 3.16.4. instant cut mode ...................................................................................................... ........34 3.16.5. short circuit protection .............................................................................................. ......34 3.16.6. thermal shutdown registers ...........................................................................................3 5 4. digital audio and control interfaces ................................................................... 37 4.1. data interface ........................................................................................................... .......................37 4.2. master and slave mode operation .......................................................................................... ........37 4.3. audio data formats ....................................................................................................... ..................38 4.4. left justified audio interface ........................................................................................... ................38 4.5. right justified audio interface (assuming n-bit wo rd length) ...........................................................38 4.6. i2s format audio interface ............................................................................................... ...............39 4.7. data interface registers ........................... ...................................................................... .................39
idt confidential 3 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 4.7.1. audio data format control register ........... .......................................................................39 4.7.2. audio interface output tri-state ................ ....................................................................... ..40 4.7.3. audio interface control 3 register ............ ......................................................................... 40 4.8. bit clock mode ........................................................................................................... ......................40 4.9. control interface ........................................................................................................ ......................41 4.9.1. register write cycle ................................................................................................... .......41 4.9.2. multiple write cycle ................................................................................................... ........42 4.9.3. register read cycle .................................................................................................... ......42 4.9.4. multiple read cycle ...... .............................................................................................. .......42 4.9.5. device addressing and identification .......... .............. .............. ............ ........... ........... .........43 5. audio clock generation ............................................................................................... 44 5.1. internal clock generation .. .............................................................................................. ................44 5.2. clocking and sample rates ................................................................................................ ............44 6. characteristics ............................................................................................................ ... 46 6.1. electrical specifications ......................... ....................................................................... ...................46 6.1.1. absolute maximum ratings ............................................................................................... 46 6.1.2. recommended operating conditions ................................................................................46 6.2. device characteristics ................................................................................................... ..................47 6.3. typical power consumption .......................... ...................................................................... ............48 6.4. low power mode power consumpt ion ............. .............. .............. .............. ........... ........... ............ ...48 7. register map ............................................................................................................... ....... 49 8. pin information ............................................................................................................ ..... 51 8.1. acs32201 tag pinout ......... .............. .............. .............. .............. .............. .............. ......... ..............51 8.2. acs32201 nag pin diagram ..... .............. .............. .............. .............. .............. ........... ........... .........52 8.3. acs32201tag pin tables ......... .............. .............. .............. .............. .............. ........... ......... ...........53 8.3.1. acs32201tag power pins ..... .............. .............. .............. .............. .............. ........... .........53 8.3.2. acs32201 tag reference pins ............... .............. .............. .............. ........... ........... .........53 8.3.3. acs32201 tag analog output pins ............. .............. .............. .............. .............. ............53 8.3.4. acs32201 tag data and control pins ......... .............. .............. .............. .............. ............54 8.3.5. acs32201 tag clock pins .. .............. .............. .............. .............. .............. .............. .........5 4 8.4. acs32201 nag pin tables ..... .............. .............. .............. .............. .............. .............. ......... ...........55 8.4.1. acs32201 nag power pins . .............. .............. .............. .............. .............. .............. .........55 8.4.2. acs32201 nag reference pins .............. .............. .............. .............. ........... ........... .........55 8.4.3. acs32201 nag analog output pins ............. .............. .............. .............. .............. ............55 8.4.4. acs32201 nag data and control pins ......... .............. .............. .............. .............. ............56 8.4.5. acs32201 nag clock pins ..... .............. .............. .............. .............. .............. ........... .........5 6 9. package information ..................................................................................................... 57 9.1. package drawing .......................................................................................................... ...................57 9.2. pb free process- package classification reflow temperatures ....................................................57 10. nag/hla package information ................................................................................. 58 10.1. nag/hla package drawing ................................................................................................. .........58 10.2. pb free process- package classification reflow temperatures ..................................................58 11. ordering information ................................................................................................. 59 12. disclaimer ................................................................................................................ ......... 59 13. document revision history ....................................................................................... 60
idt confidential 1 v0.8 04/11 ?2011 integrated device technology, inc. acs422x68 acs422x68 low-power, high-fidelit y, class-d amplifier list of tables table 1. power management register 1 .............. .............. .............. .............. .............. ........... ......... ................3 table 2. power management register 2 .............. .............. .............. .............. .............. ........... ......... ................3 table 3. power management register1 -- master clock dis able ............ .............. .............. .............. ............. .3 table 4. dc_coef_sel register ................................................................................................. ..................4 table 5. config0 register ..................................................................................................... ........................4 table 6. volume update control regi ster ....................................................................................... ................5 table 7. gain control register ....................... ......................................................................... .........................5 table 8. dac volume control registers ................. ........................................................................ .................6 table 9. config1 register ..................................................................................................... ........................7 table 10. daccram read/write regist ers ............ .............. .............. .............. ............ ........... .......... ............8 table 11. daccram address register .............. .............. .............. .............. .............. ........... ........... ..............8 table 12. daccram status register .............. .............. .............. .............. .............. .............. ......... ................8 table 13. daccram eq addresess ..... .............. .............. .............. .............. .............. ........... .......... .............11 table 14. daccram bass/treble addresse s ............. .............. .............. .............. ........... ............ ......... ........12 table 15. clectl register ........ ............................................................................................. ......................17 table 16. mugain register ................................ ..................................................................... .....................17 table 17. compth register ..................................................................................................... ....................17 table 18. cmprat register ..................................................................................................... .....................17 table 19. catktcl register .................................................................................................... ....................17 table 20. catktch register .................................................................................................... ....................18 table 21. creltcl register .................................................................................................... ....................18 table 22. creltch register .................................................................................................... ....................18 table 23. limth register ...................................................................................................... ........................18 table 24. limtgt register ..................................................................................................... .......................18 table 25. latktcl register .................................................................................................... .....................18 table 26. latktch register .................................................................................................... ....................18 table 27. lreltcl register .................................................................................................... .....................18 table 28. lreltch register .................................................................................................... ....................19 table 29. expth register . .............. .............. .............. .............. ........... ............ ........... ........... .......................19 table 30. exprat register ............ .............. .............. .............. .............. ........... ............ .......... .....................19 table 31. xatktcl register .................................................................................................... .....................19 table 32. xatktch register .................................................................................................... ....................19 table 33. xreltcl register ........ ............................................................................................ .....................19 table 34. xreltch register .................................................................................................... ....................19 table 35. fx control register ................................................................................................. .......................20 table 36. cnvrtr1 register .............................. ...................................................................... ....................24 table 37. spkvol l/r registers ....... .............. .............. .............. .............. ........... ........... ........... ..................25 table 38. constant output power 1 register ........... ......................................................................... ............28 table 39. constant output power 2 register ........... ......................................................................... ............29 table 40. constant output power 3 register ........... ......................................................................... ............29 table 41. config0 register .................................................................................................... .....................29 table 42. pwm0 register ....................................................................................................... .......................30 table 43. pwm1 register ....................................................................................................... .......................30 table 44. pwm2 register ....................................................................................................... .......................30 table 45. pwm3 register ....................................................................................................... .......................30 table 46. power management 2 register ......................................................................................... .............31 table 47. additional control register ............ .............. .............. .............. .............. ........... .......... ...................32 table 48. speaker operation ................................................................................................... ......................32 table 49. additional control register ............ .............. .............. .............. .............. ........... .......... ...................35 table 50. thermts register .................................................................................................... ...................35 table 51. thermtspkr1 register ...... .............. .............. .............. .............. .............. ........... ......... ..............36 table 52. thermtspkr2 register ...... .............. .............. .............. .............. .............. ........... ......... ..............36 table 53. aic1 register ....................................................................................................... ..........................39 table 54. aic2 register ....................................................................................................... ..........................40 table 55. aic3 register ....................................................................................................... ..........................40 table 56. master mode bclk frequency control register ......................................................................... ..40 table 57. devadrl register ........... .............. .............. .............. .............. ........... ............ .......... .....................43 table 58. devid h&l registers ................................................................................................. ...................43
idt confidential 2 v0.8 04/11 ?2011 integrated device technology, inc. acs422x68 acs422x68 low-power, high-fidelit y, class-d amplifier table 59. revid register ...................................................................................................... ........................43 table 60. reset register ............ .............. .............. .............. .............. ............ ........... ........... .......................43 table 61. dacsr register ...................................................................................................... ......................44 table 62. master clock and sample ra tes .......... .............. .............. .............. .............. ........... .......... .............44 table 63. electrical specification: maximum ratings ........................................................................... .........46 table 64. recommended operating conditions .................................................................................... ........46 table 65. device characteristics ......................... ..................................................................... .....................47 table 66. typical power consumption ..................... ...................................................................... ...............48 table 67. low power mode power consumption ............. .............. .............. ........... ........... ............ ......... ........48 table 68. register map ........................................................................................................ ..........................49 table 69. acs32201 tag power pins ............. .............. .............. .............. .............. .............. .......... .............53 table 70. acs32201 tag reference pins ............. .............. .............. .............. .............. ........... ......... ...........53 table 71. acs32201 tag analog output pins ........ .............. .............. .............. .............. ............ ......... ........53 table 72. acs32201 tag data and control pins .......... .............. .............. ........... ........... ............ .......... .......54 table 73. acs32201 tag clock pins ... .............. .............. .............. .............. .............. ........... ......... ..............54 table 74. acs32201 nag power pins ............. .............. .............. .............. .............. .............. .......... .............55 table 75. acs32201 nag reference pi ns .............. .............. .............. .............. ............ ........... .......... ..........55 table 76. acs32201 nag analog output pins .............. .............. .............. ........... ........... ............ ......... ........55 table 77. acs32201 nag data and control pins .......... .............. .............. ........... ........... ............ .......... .......56 table 78. acs32201 nag clock pins .............. .............. .............. .............. .............. .............. ......... ..............56 table 79. reflow temperatures .. ............................................................................................... ....................57 table 80. reflow temperatures .. ............................................................................................... ....................58
idt confidential 1 v0.8 04/11 ?2011 integrated device technology, inc. acs422x68 acs422x68 low-power, high-fidelit y, class-d amplifier list of figures figure 1. acs32201 block diagram ... .............. .............. .............. .............. .............. ........... .......... ..................2 figure 2. output audio processing ............................................................................................. .....................4 figure 3. prescaler & eq filters .............................................................................................. ........................6 figure 4. 6-tap iir equalizer filter .......................................................................................... ........................7 figure 5. dac coefficient ram write sequence .................................................................................. ...........9 figure 6. dac coefficient ram read sequence ................................................................................... ........10 figure 7. gain compressor, output vs input .................................................................................... .............13 figure 8. compressor block diagram ...................... ...................................................................... .................15 figure 9. 3-d channel inversion .......................... ..................................................................... .....................20 figure 10. bass enhancement ................................................................................................... ....................21 figure 11. treble enhancement ................................................................................................. ...................23 figure 12. constant output power error ................. ....................................................................... ................27 figure 13. constant output power nominal and high/low .. .............. .............. ........... ........... ........... .......... .....28 figure 14. temp sense volume adjustment algorithm . ............................................................................ ......34 figure 15. master mode ........................................................................................................ .........................37 figure 16. slave mode ......................................................................................................... ..........................37 figure 17. left justified audio interface (assuming n-bit wo rd length) ....... .............. .............. ........... .......... ..38 figure 18. right justified audio interface (assuming n-bi t word length) ....................................................... .38 figure 19. i2s justified audio interface (assuming n-bit wo rd length) ........ .............. .............. ........... .......... ..39 figure 20. bit clock mode ..................................................................................................... .........................41 figure 21. 2-wire serial control interface ............ ........................................................................ ..................41 figure 22. multiple write cycle ......................... ...................................................................... .......................42 figure 23. read cycle ......................................................................................................... ..........................42 figure 24. multiple read cycle ... ............................................................................................. ......................43 figure 25. acs32201 tag pinout ................................................................................................ .................51 figure 26. acs32201 nag pinout ................................................................................................ ................52 figure 27. package outline .................................................................................................... .......................57 figure 28. nag/hla package outline ...................... ...................................................................... ...............58
idt confidential 2 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 1. overview 1.1. block diagrams the acs32201 is an advanced digital class-d amplifier. to support the design of audi o subsystems in a portable device, the acs32201 features an intellig ent architecture with advanced audio processing algorithms and a 1w/chan- nel filterless stereo class d amplifier. figure 1. acs32201 block diagram 1.2. audio outputs to enhance the sound available from the small, low-power sp eakers typically found in a portable device, the acs32201 provides numerous audio enhancement capabilities. the acs32201 featur es dual, independ ent, programmable left/right 6-band equalization, allowing the system designer to provide an advanced system equalizer to accommodate the specific speakers and enclosure design. a compressor /limiter features programmabl e attack and release thresh- olds, enabling the system designer to attenuate loud noise excursions to avoid speaker artifacts, thus allowing the underlying content to be played at a louder volume without distortion. for compressed audio, a programmable expander is available to help restore the dynamic range of the original content. a ster eo depth enhancement algorithm allows common left/right content (e.g. dialog) to be atten uated separately from other content, providing a perceived depth separation between background and foreground audio. psychoacoustic bass and treble enhancement algo- rithms achieve a rich, full tone even from originally comp ressed content, and even with speakers generally unable to play low-frequency sounds. pll audio processing bass/treble enhancement system eq speaker eq 3-d effect compressor-limiter dynamic range expander s o u r c e s e l e c t s w i t c h dac left class d left+ btl digital pwm controller dacin class d right+ dac right clocking control i2c_scl i2c_sda daclrclk dacbclk mclk internal audio clock(s) pvdd dvdd_core dvdd_io avdd vol btl digital pwm controller vol 4 dvss avss pvss 4 4 vref spkr_en test 4 vdd_xtal vdd_pll2 vdd_pll1 vdd_plss vss_plss vss_xtal class d left- class d right- vdd_pll3
idt confidential 3 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 2. power management 2.1. control registers the acs32201 has control registers to enable system soft ware to control which functions are active. to minimize power consumption, unused func tions should be disabled. to avoid audio artifa cts, it is important to enable or disable functions in the correct order. 2.2. stopping the master clock in order to minimize digital core power consumption, th e master clock may be stopped in standby and off modes by setting the digenb bit (r25, bit 0). note: before digenb can be se t, the control bits spkl and spkr must be set to zero and a waiting time of 100ms must be observed to allow port ramping/gain fading to complete. any failure to follow this procedure may cause pops or, if less than 1ms, may prevent the dacs from re-starting correctly. register address bit label type default description 0x1a power management 1 7:1 rsvd rw 0 reserved 0digenbrw0 master clock disable 0: master clock enabled, 1: master clock disabled table 1. power management register 1 register address bit label type default description 0x1b power management 2 7:5 rsvd rw 0 reserved 4 spkl rw 0 lspk output buffer 0 = power down, 1 = power up 3 spkr rw 0 rspk output buffer 0 = power down, 1 = power up 2:1 rsvd rw 0 reserved 0vrefrw0 vref (necessary for all other functions) 0 = power down, 1 = power up table 2. power management register 2 register address bit label type default description 0x1a power management 1 0digenbrw0 master clock disable 0 = master clock enabled, 1 = master clock disabled table 3. power management register1 -- master clock disable
idt confidential 4 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3. output audio processing figure 2. output audio processing 3.1. dc removal before processing, a dc removal filter removes the dc co mponent from the incoming audio data. the dc removal fil- ter is programmable. register address bit label type default description r65 (41h) dcofsel 7:3 ? r 0 reserved for future use. 2:0 - rw 5 0: dc_coef = 24'h100000; //2^^-3 = 0.125 1: dc_coef = 24'h040000; 2: dc_coef = 24'h010000; 3: dc_coef = 24'h004000; 4: dc_coef = 24'h001000; 5: dc_coef = 24'h000400; 6: dc_coef = 24'h000100; //2^^-15 = 0.00030517 7: dc_coef = 24'h000040; //2^^-17 table 4. dc_coef_sel register register address bit label type default description r31 (1fh) config0 7:2 rsvd rw 10h reserved 1 dc_bypass rw 0 1 = bypass dc removal filter (warning dc content can damage btl output) 0 rsvd r 0 reserved table 5. config0 register dc removal eq1 eq2 compressor limiter expander prescale 1 prescale 2 gain 33h ? 38h 25h 2dh ? 32h limiter expander control 0 to 46.5 db in 1.5 db steps 3dh ? 3fh 3ah ? 3ch write read 40h address 8ah status daccram 80h ? 96h bass coefficients daccram 97h ? adh treble coefficients phase invert dac volume mute 0 to -95.25db 0.375db steps 18h dacpol 04h ? 05h dac volume dac_l/r 18h mute de- emphasis 18h de-emphasis 39h fxctrl 41h dc-coef_sel daccram 00h ? 3dh eq1 coefficients daccram 40h ? 7dh eq2 coefficients 26h ? 2ch compressor pa bass pa treble 3-d daccram aeh ? afh 3d coefficients daccram afh daccram 96h daccram adh mono mix 18h dmonomix class d left btl digital pwm controller left spkr vol audio processing bass/treble enhancement system eq speaker eq 3-d effect compressor-limiter dynamic range expander 02h +12 to -77.25 db in 0.75 db steps thermal limit 1bh btl power management interpolation dac_l/r class d right btl digital pwm controller spkr vol 03h +12 to -77.25 db in 0.75 db steps thermal limit 1bh btl power management right 1ch ? 1eh 88h 1ch ? 1eh 88h
idt confidential 5 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.2. volume control the signal volume can be controlled digitally, across a gain and attenuation range of -95.25db to 0db (0.375db steps). the level of attenuation is specified by an eight-bit code, ?dacvol_x?, where ?x? is l, or r. the value ?00000000? indi- cates mute; other values select the number of 0. 375db steps above -95.625db for the volume level. the volume update bits control the updating of volume contro l data; when a bit is written as ?0?, the left volume control associated with that bit is updated whenever the left volume register is written and the right volume control is updated when ever the right volume register is written. when a bit is written as ?1?, the left volume data is placed into an internal holding register when the left volume register is written and both the left and right volumes are updated when the right volume register is written. this enables a simultaneous left and right volume update the output path may be muted automatically when a long string of zero data is received. the length of zeros is pro- grammable and a detection flag indicates when a stream of zero data has been detected. register address bit label type default description r10 (0ah) vuctl 7 rsvd rw 1 reserved 6 dacfade rw 1 1 = volume fades between old/new value 0 = volume/mute changes immediately 5:3 rsvd r 0 reserved for future use. 2 dacvolu rw 0 0 = left dac volume updated immediately 1 = left dac volume held until right dac volume register written. 1 spkvolu rw 0 0 = left speaker volume updated immediately 1 = left speaker volume held until right speaker volume register written. 0 rsvd rw 0 reserved table 6. volume update control register register address bit label type default description r33 (21h) gain control (gainctl) 7 zerodet_flag r 0 1 = zero detect length exceeded. 6 rsvd r 0 reserved for future use. 5:4 zerodetlen rw 2 enable mute if input consecutive zeros exceeds this length. 0 = 512, 1 = 1k, 2 = 2k, 3 = 4k samples 3 rsvd r 0 reserved for future use. 2 auto_mute rw 1 1 = auto mute if detect long string of zeros on input 1 rsvd r 0 reserved for future use. 0 rsvd r 0 reserved for future use. 7 zerodet_flag r 0 1 = zero detect length exceeded. table 7. gain control register
idt confidential 6 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.3. digital dac volume control the signal volume can be controlled digitally, across a gain and attenuation range of -95.25db to 0db (0.375db steps). the level of attenuation is specified by an eight-bit code, ?dacvol_x?, where ?x? is l, or r. the value ?00000000? indi- cates mute; other values select the number of 0. 375db steps above -95.625db for the volume level. 3.4. parametric equalizer the acs32201 has a dual 6-band digital parametric equalizer to enable fine tuning of the audio response and prefer- ences for a given system. each eq ma y be enabled or disabled independently. typically one eq will be used for speaker compensation and disabled when only headphones ar e in use while the other eq is used to alter the audio to make it more pleasing to the listener. this function operates on the digital audio data before it is converted back to ana- log by the audio dacs. in all, 186 bytes of memory are required to store the paramete rs for each equalizer: each filter requires 5, 24-bit coeffi- cients. there are 6 filters per channel, requiring a total of 180 bytes of eq coefficient ram. two additional 24-bit values per channel store the prescale value, resulting in 372 bytes to tal, described later. rather than having all 372 bytes be in the i2c address space of the device, access to the eq ram occurs through the control/status registers. 3.4.1. prescaler & equalizer filter the equalizer filter consists of a prescaler and 6 cascaded 6-tap iir filters. the prescaler allows the input to be attenuated prior to the eq filters in case the eq filters introduce gain, and would thus clip if not prescaled. idt provides a tool to enable an audio designer to determine appropriate coefficients for the equal- izer filters. the filters enable the implementation of a 6-band parametric equalizer with selectable fre- quency bands, gain, and filter characteristics (high, low, or bandpass). figure 3. prescaler & eq filters register address bit label type default description r4 (04h) left dac volume control 7:0 dacvol_l [7:0] rw ff (0db) left dac volume level 0000 0000 = digital mute 0000 0001 = -95.25db 0000 0010 = -94.875db ... 0.375db steps up to 1111 1111 = 0db note: if dacvolu is set, this setting will take effect after the next write to the right input volume register. r5 (05h) right dac volume control 7:0 dacvol_r [7:0] rw ff (0db) right dac digital volume level 0000 0000 = digital mute 0000 0001 = -95.25db 0000 0010 = -94.875db ... 0.375db steps up to 1111 1111 = 0db table 8. dac volume control registers data in eq_prescale eq filter 0 data out eq filter 1 eq filter 2 eq filter 3 eq filter 4 eq filter 5
idt confidential 7 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier the figure below shows the structure of a single eq filter. the a(0) tap is always normalized to be equal to 1 (400000h). the remaining 5 taps are 24-bit twos compliment format programmable coeffi- cients. (-2 coefficient < +2). figure 4. 6-tap iir equalizer filter 3.4.2. eq registers ? eq filter enable register register address bit label type default description r32 (20h) config1 7 eq2_en r/w 0 eq bank 2 enable 0 = second eq bypassed, 1 = second eq enabled 6:4 eq2_be[2:0] r/w 0 eq2 band enable. when the eq is enabled the following eq stages are executed. 0 - prescale only 1 - prescale and filter band 0 ... 6 - prescale and filter bands 0 to 5 7 - reserved 3 eq1_en r/w 0 eq bank 1 enable 0 = first eq bypassed, 1 = first eq enabled 2:0 eq1_be[2:0] r/w 0 eq1 band enable. when the eq is enabled the following eq stages are executed. 0 - prescale only 1 - prescale and filter band 0 ... 6 - prescale and filter bands 0 to 5 7 - reserved table 9. config1 register z -1 x(n) b(0) *2 b(1) *2 b(2) z -1 z -1 z -1 y(n) a(1) *2 a(2) z -1 x(n) b(0) b(1) b(2) z -1 z -1 z -1 y(n) a(1) a(2)
idt confidential 8 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier ? daccram read data (0x3d?lo, 0x3e ?mid, 0x3f?hi), daccram write da ta (0x3a?lo, 0x3b?mid, 0x3c?hi) registers these two 24-bit registers provide the 24-bit data holding registers used when doing indire ct writes/reads to the dac coefficient ram. ? daccram address register this 7-bit register provides the address to the internal ra m when doing indirect writes/r eads to the dac coefficient ram. ? daccram status register this control register provides the write/read enable when doing indirect writes/reads to the dac coefficient ram. register address bit label type default description r58 (3ah) daccram_write_lo 7:0 daccrwd[7:0] r/w 0 low byte of a 24-bit data register, contains the values to be written to the daccram. the address written will have been specified by the daccram address fields. r59 (3bh) daccram_write_mid 7:0 daccrwd[15:8] r/w 0 middle byte of a 24-bit data register, contains the values to be written to the daccram. the address written will have been specified by the daccram address fields. r60 (3ch) daccram_write_hi 7:0 daccrwd[23:16] r/w 0 high byte of a 24-bit data register, contains the values to be written to the daccram. the address written will have been specified by the daccram address fields. r61 (3dh) daccram_read_lo 7:0 daccrrd[7:0] r 0 low byte of a 24-bit data register, contains the contents of the most recent daccram address read from the ram. the address read will ha ve been specified by the daccram address fields. r62 (3eh) daccram_read_mid 7:0 daccrrd[15:8] r 0 middle byte of a 24-bit data register, contains the contents of the most recent daccram address read from the ram. the address read will have been specified by the daccram address fields. r63 (3fh) daccram_read_hi 7:0 daccrrd[23:16] r 0 high byte of a 24-bit data register, contains the contents of the most recent daccram address read from the ram. the address read will have been specified by the daccram address fields. table 10. daccram read/write registers register address bit label type default description r64 (40h) daccraddr 7:0 daccradd r/w 0 contains the address (between 0 and 255) of the daccram to be accessed by a read or write. this is not a byte address--it is the address of the 24-bit data item to be access ed from the daccram.this address is automatically incremented after writing to daccram_write_hi or reading from daccram_read_hi (and the 24 bit data from the next ram location is fetched.) table 11. daccram address register register address bit label type default description r138 (8ah) daccrstat 7 daccram_busy r 0 1 = read/write to daccram in progress, cleared by hw when done. 6:0 rsvd r 0 reserved table 12. daccram status register
idt confidential 9 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.4.3. equalizer, bass, treble coefficient & equalizer prescaler ram the dac coefficient ram is a single port 161x24 synchronous ram. it is programmed indirectly through the control bus in the following manner: 1. write target address to daccram_addr register. 2. write d7:0 to the daccram_write_lo register 3. write d15:8 to the da ccram_write_mid register 4. write d23:16 to the daccram_write_hi register 5. on successful receipt of the daccram_write_hi data, the part will automatically start a write cycle. the daccram_busy bit will be set high to indicate that a write is in progress. 6. on completion of the internal write cycle, the daccram_busy bit will be 0 (when op erating the control interface at high speeds - tbd - software must poll this bit to ensure the write cycle is complete before starting another write cycle.) 7. the bus cycle may be terminated by the host or steps 2-6 may be repeated for writes to consec- utive eq ram locations. figure 5. dac coeffi cient ram write sequence reading back a value from the daccram is done in this manner: 1. write target address to daccram_addr register.( eq data is pre-fetched for read even if we don?t use it) 2. start (or repeat start) a write cycle to daccram _read_lo and after the second byte (register address) is acknowledged, go to step 3. (do not complete the write cycle.) 3. signal a repeat start and indicate a read operation 4. read d7:0 (register address incremented after ack by host) 5. read d15:8 (register address incremented after ack by host) 6. read d23:16 (register address incremented and ne xt eq location pre-fetched after ack by host) 7. the host stops the bus cycle to repeat a read cycle for consecutive eq ram locations: 1. start (or repeat start instead of stopping the bus cycle in step 7) a write cycle indicating daccram_rd_lo as the target address. 2. after the second byte is acknowledged, signal a repeated start. 3. indicate a read operation 4. read the daccram_read_lo regist er as described in step 4 da6 da0 s w a s scl ra1 ra0 a s ra7 rd7 rd0 a s sda register write here writing 1 reigster register write here 28 scl cycles 70 us min. da[6:0], w 2.5 us min. s ra[7:0] rd[7:0] write eq ram address write eq ram write lo write eq ram write mid write eq ram write hi write eq ram write lo eq ram write req = 1 eq ram write must have finished here; eq_a ++ eq ram write lo updated here generic write operation eq ram write operation repeat for multiple consecutive eq ram locations writes eq_a updated; eq ram read req = 1 eq ram read finished; eq read data valid (time not fixed) p s da[6:0], w ra[7:0] rd[7:0] rd[7:0] rd[7:0] s da[6:0], w ra[7:0] rd[7:0] rd[7:0] write eq ram write mid rd7 rd0 a s multiple write cycle rd7 rd0 a s multiple write cycle
idt confidential 10 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 5. read the daccram_read_mid regi ster as described in step 5 6. read the daccram_read_hi register as described in step 6 7. repeat steps 8-13 as desired figure 6. dac coefficient ram read sequence ? daccram eq addresess eq 0 eq1 addr channel 0 coefficients addr channel 1 coefficients addr channel 0 coefficients addr channel 1 coefficients 0x00 eq_coef_0f0_b0 0x20 eq_coef_1f0_b0 0x40 eq_coef_2f0_b0 0x60 eq_coef_3f0_b0 0x01 eq_coef_0f0_b1 0x21 eq_coef_1f0_b1 0x41 eq_coef_2f0_b1 0x61 eq_coef_3f0_b1 0x02 eq_coef_0f0_b2 0x22 eq_coef_1f0_b2 0x42 eq_coef_2f0_b2 0x62 eq_coef_3f0_b2 0x03 eq_coef_0f0_a1 0x23 eq_coef_1f0_a1 0x43 eq_coef_2f0_a1 0x63 eq_coef_3f0_a1 0x04 eq_coef_0f0_a2 0x24 eq_coef_1f0_a2 0x44 eq_coef_2f0_a2 0x64 eq_coef_3f0_a2 0x05 eq_coef_0f1_b0 0x25 eq_coef_1f1_b0 0x45 eq_coef_2f1_b0 0x65 eq_coef_3f1_b0 0x06 eq_coef_0f1_b1 0x26 eq_coef_1f1_b1 0x46 eq_coef_2f1_b1 0x66 eq_coef_3f1_b1 0x07 eq_coef_0f1_b2 0x27 eq_coef_1f1_b2 0x47 eq_coef_2f1_b2 0x67 eq_coef_3f1_b2 0x08 eq_coef_0f1_a1 0x28 eq_coef_1f1_a1 0x48 eq_coef_2f1_a1 0x68 eq_coef_3f1_a1 0x09 eq_coef_0f1_a2 0x29 eq_coef_1f1_a2 0x49 eq_coef_2f1_a2 0x69 eq_coef_3f1_a2 0x0a eq_coef_0f2_b0 0x2a eq_coef_1f2_b0 0x4a eq_coef_2f2_b0 0x6a eq_coef_3f2_b0 0x0b eq_coef_0f2_b1 0x2b eq_coef_1f2_b1 0x4b eq_coef_2f2_b1 0x6b eq_coef_3f2_b1 0x0c eq_coef_0f2_b2 0x2c eq_coef_1f2_b2 0x4c eq_coef_2f2_b2 0x6c eq_coef_3f2_b2 0x0d eq_coef_0f2_a1 0x2d eq_coef_1f2_a1 0x4d eq_coef_2f2_a1 0x6d eq_coef_3f2_a1 0x0e eq_coef_0f2_a2 0x2e eq_coef_1f2_a2 0x4e eq_coef_2f2_a2 0x6e eq_coef_3f2_a2 0x0f eq_coef_0f3_b0 0x2f eq_coef_1f3_b0 0x4f eq_coef_2f3_b0 0x6f eq_coef_3f3_b0 0x10 eq_coef_0f3_b1 0x30 eq_coef_1f3_b1 0x50 eq_coef_2f3_b1 0x70 eq_coef_3f3_b1 ra1 da6 a s da0 rd7 s r r a s rd0 a m ra7 1. da: device address 6. a m : acknowledge from master 2. ra: register address 7. n m : not acknowledge from master 3. eq_a: eq ram address 8. s: start 4. rd: register data 9. s r : repeated start 5. a s : acknowledge from slave 10. p: stop scl sda da[6:0], w s ra[7:0] rd[7:0] write eq ram address rd[7:0] read eq ram data lo read eq ram data mid read eq ram data hi eq_a ++; prefetch data da[6:0], r s r rd[7:0] ra[7:0] write eq ram read lo , truncate s p da[6:0], w eq ram data must be valid here generic read operation eq ram read operation eq_a updated; eq ram read req = 1 30 scl cycles 75 us min. repeat for multiple consecutive eq ram locations reads ra0 rd7 rd0 a m rd7 rd0 n m multiple read cycle read 1 register multiple read cycle rd[7:0] s r ra[7:0] write eq ram read lo, truncate s da[6:0], w p rd[7:0] read eq ram data lo da[6:0], r eq ram data must be valid here nack from master to end read cycle
idt confidential 11 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier table 13. daccram eq addresess ? daccram bass/treble addresses 0x11 eq_coef_0f3_b2 0x31 eq_coef_1f3_b2 0x51 eq_coef_2f3_b2 0x71 eq_coef_3f3_b2 0x12 eq_coef_0f3_a1 0x32 eq_coef_1f3_a1 0x52 eq_coef_2f3_a1 0x72 eq_coef_3f3_a1 0x13 eq_coef_0f3_a2 0x33 eq_coef_1f3_a2 0x53 eq_coef_2f3_a2 0x73 eq_coef_3f3_a2 0x14 eq_coef_0f4_b0 0x34 eq_coef_1f4_b0 0x54 eq_coef_2f4_b0 0x74 eq_coef_3f4_b0 0x15 eq_coef_0f4_b1 0x35 eq_coef_1f4_b1 0x55 eq_coef_2f4_b1 0x75 eq_coef_3f4_b1 0x16 eq_coef_0f4_b2 0x36 eq_coef_1f4_b2 0x56 eq_coef_2f4_b2 0x76 eq_coef_3f4_b2 0x17 eq_coef_0f4_a1 0x37 eq_coef_1f4_a1 0x57 eq_coef_2f4_a1 0x77 eq_coef_3f4_a1 0x18 eq_coef_0f4_a2 0x38 eq_coef_1f4_a2 0x58 eq_coef_2f4_a2 0x78 eq_coef_3f4_a2 0x19 eq_coef_0f5_b0 0x39 eq_coef_1f5_b0 0x59 eq_coef_2f5_b0 0x79 eq_coef_3f5_b0 0x1a eq_coef_0f5_b1 0x3a eq_coef_1f5_b1 0x5a eq_coef_2f5_b1 0x7a eq_coef_3f5_b1 0x1b eq_coef_0f5_b2 0x3b eq_coef_1f5_b2 0x5b eq_coef_2f5_b2 0x7b eq_coef_3f5_b2 0x1c eq_coef_0f5_a1 0x3c eq_coef_1f5_a1 0x5c eq_coef_2f5_a1 0x7c eq_coef_3f5_a1 0x1d eq_coef_0f5_a2 0x3d eq_coef_1f5_a2 0x5d eq_coef_2f5_a2 0x7d eq_coef_3f5_a2 0x1e - 0x3e - 0x5e - 0x7e - 0x1f eq_prescale0 0x3f eq_prescale1 0x5f eq_prescale2 0x7f eq_prescale3 addr bass coefficients 1 addr treble coefficients addr 3d coefficients 0x80 bass_coef_ext1_b0 0x97 tr eb_coef_ext1_b0 0xae 3d_coef 0x81 bass_coef_ext1_b1 0x98 tr eb_coef_ext1_b1 0xaf 3d_mix 0x82 bass_coef_ext1_b2 0x 99 treb_coef_ext1_b2 0x83 bass_coef_ext1_a1 0x9a treb_coef_ext1_a1 0x84 bass_coef_ext1_a2 0x9b treb_coef_ext1_a2 0x85 bass_coef_ext2_b0 0x9c treb_coef_ext2_b0 0x86 bass_coef_ext2_b1 0x9d treb_coef_ext2_b1 0x87 bass_coef_ext2_b2 0x9e treb_coef_ext2_b2 0x88 bass_coef_ext2_a1 0x9f treb_coef_ext2_a1 0x89 bass_coef_ext2_a2 0xa0 treb_coef_ext2_a2 0x8a bass_coef_nlf_m1 2 0xa1 treb_coef_nlf_m1 0x8b bass_coef_nlf_m2 0xa2 treb_coef_nlf_m2 0x8c bass_coef_lmt_b0 0xa3 treb_coef_lmt_b0 eq 0 eq1 addr channel 0 coefficients addr channel 1 coefficients addr channel 0 coefficients addr channel 1 coefficients
idt confidential 12 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier table 14. daccram bass/treble addresses 3.5. gain and dynamic range control the gain for a given channel is controlled by the dacvol re gisters. the range of gain su pported is from -95.625db to 0db in 0.375db steps. if the result of the gain multiply step w ould result in overflow of the 24-bit output word width, the output is saturated at the max positive or negative value. in addition to simple gain control, the acs32201 also provides sophisticated dynamic range control. the dynamic range control processing element implements limiting, dynamic range compression, and dynamic range expansion functions. 3.6. limiter the limiter function will limit the output of the dsp module to the class-d an d dac modules. if the signal is greater than 0db it will saturate at 0db as the fi nal processing step wit hin the dsp module. there are times when the user may intentionally want the outp ut limiter to perform this sa turation, for example +6db of gain applied within the dsp gain control and then limited to 0db when output to the class-d module would result in a clipped signal driving the speaker outpu t. this clipped signal would obviously c ontribute to increased distortion on the speaker output which from the user listeni ng perception it would ?sound louder?. at other times, the system implementor may wish to protect speakers from overheating or provide hearing protection by intentionally limiting th e output level before full scale is reached. a limit threshold, independent of the compressor threshold is provided for this purpose. it is expected that th e limit threshold is set to a higher level than the compressor threshold. 0x8d bass_coef_lmt_b1 0xa4 treb_coef_lmt_b1 0x8e bass_coef_lmt_b2 0xa5 treb_coef_lmt_b2 0x8f bass_coef_lmt_a1 0xa6 treb_coef_lmt_a1 0x90 bass_coef_lmt_a2 0xa7 treb_coef_lmt_a2 0x91 bass_coef_cto_b0 0xa8 treb_coef_cto_b0 0x92 bass_coef_cto_b1 0xa9 treb_coef_cto_b1 0x93 bass_coef_cto_b2 0xaa treb_coef_cto_b2 0x94 bass_coef_cto_a1 0xab treb_coef_cto_a1 0x95 bass_coef_cto_a2 0xac treb_coef_cto_a2 0x96 bass_mix 0xad treb_mix 1.all b0 coefficients are set to unit y (400000h) by default. all others, in cluding m1 and m2, are 0 by default. 2.nlf coefficients (m1, m2) have a range defined as +/-8, with 1 sign bit, 3 integer bits, and 20 fraction bits. so, unity for these values is 100000h. this is as opposed to the rest of the coefficient ram, which has a range defined as +/-2, with 1 sign bit, 1 integer bit, and 22 fraction bits. addr bass coefficients 1 addr treble coefficients addr 3d coefficients
idt confidential 13 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.7. compressor figure 7. gain compressor, output vs input the traditional compressor algorithm pr ovides two functions simultaneously (depending on signal level). for higher level signals, it can provide a compression function to reduce the signal level. for lower le vel signals, it can provide an expansion function for either increa sing dynamic range or noise gating. the compressor monitors the si gnal level and, if the signal is higher than a threshold, will reduce the gain by a pro- grammed ratio to restrict the dynamic range. limiting is an extreme example of the compress or where, as the input sig- nal level is increased, the gain is decrea sed to maintain a specific output level. in addition to limiting the bandwidth of the compressed audi o, it is common for compress ed audio to also compress the dynamic range of the audio. the expansion function in t he acs32201 can help restore the original dynamics to the audio. the expander is a close relative of the compressor. rather than using signal dependent gain to restrict the dynamic range, the expander uses signal dependent gain to expand the dynamic range. thus if a signal level is below a particu- lar threshold, the expander will reduce the gain even further to extend the dynamic range of the material. output (dbfs) it(dbfs) 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -16 -18 -20 -22 -14 -12 -10 -8 -6 -4 -2 0 limit threshold: compressor threshold: compressor ratio: 3:1 -14.25 dbfs -6 dbfs expander threshold: -18 dbfs expander ratio: 1:2 expanded output range natural output range compressed output range compressor threshold expander threshold limit threshold
idt confidential 14 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.7.1. configuration this compressor limiter provides th e following configurable parameters. ? compressor/limiter ? threshold ? the threshold ab ove which the compressor will re duce the dynamic range of the audio in the compression region. ? ratio ? the ratio between the input dynamic range and the output dynamic range. for example, a ratio of 3 will reduce an input dynamic range of 9db to 3db. ? attack time ? the amount of time that changes in gain are smoothed over during the attack phase of the compressor. ? release time ? the amount of time that changes in gain are smoothed over during the release phase of the compressor. ? makeup gain ? used to increase the overall level of the compressed audio. ? expander ? threshold ? the threshold below which the ex pander will increase the dynamic range of the audio. ? ratio ? the ratio between the input dynamic range and the output dynamic range of the audio in the expansion range. for example a ratio of 3 will take an input dynamic range of 9db and expand it to 27db. ? attack time ? the amount of time that changes in gain are smoothed over during the attack phase of the expander ?release time ? - the amount of time that changes in gain are smoothed over during the release phase of the expander. ? two level detection algorithms ? rms ? use an rms measurement for the level. ? peak ? use a peak measurement for the level. 3.7.2. controlling parameters in order to control this processing, there are a number of configurable parameters. the parameters and their ranges are: ? compressor/limiter ? threshold ? -40db to 0db relative to full scale. ? ratio ? 1 to 20 ? attack time ? typically 0 to 500ms ? release time ? typically 25ms to 2 seconds ? makeup gain ? 0 to 40db ? expander ? threshold ? -30 to -60 db ? ratio ? 1 to 6 ? attack time ? same as above ? release time ? same as above. ? two level detection algorithms ?rms ?peak
idt confidential 15 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.7.3. overview a basic block diagram of the compressor is shown below: figure 8. compressor block diagram as this diagram shows, there are 3 primary components of the compressor. 1. level detector: the level detector, oddly enough, detects the level of the incoming signal. since the comp/limiter is designed to work on blocks of signals, t he level detector will either find the peak value of the block of samples to be processed or the rms level of the samples within a block. 2. gain calculation: the gain calculation block is responsible for taking the output of the level detector and calculating a target gain based on that level and the compressor and expander thresholds. the compressor recalculates the ta rget gain value every block, typically every 10ms. ? the gain calculation operates in 3 regions: ? linear region ? if the level is higher th an the expander threshold and lower than the compression threshold, then the gain is 1.0 ? compression region ? when the level is higher than the compressor threshold, then the comp/limiter is in the compress ion region. the gain is a function of the compressor ratio and the signal level. ? expansion region ? when the signal is lower than the expansion threshold, the comp/limiter is in the expansion region. in this region, the gain is a function of the signal level and the expansion ratio. ? compression region gain calculation: in the compression region, the gain calculation is: atten(in db) = (1-1/ratio)(threshold(in db) ? level(in db); ? for example, ? ratio = 4:1 compression ? threshold = -16db ? level = -4 db the required attenuation is: 9db or a gain coefficient of 0.1259. translating this calculation from log space to linear yields the formula: gain =(level/threshold) 1/ratio *(threshold/level) ? expansion region gain calculation: in the ex pansion region, the attenuation calculation is: level detector gain calc attack/ release filter peak or rms compare to thresholds calc gain lowpass filter gains based on attack and release audio in audio out
idt confidential 16 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier atten(in db) = (1 - ratio)(threshold-level); ? for example, ? ratio = 3:1 ? threshold = -40db ? level = -44 db the resulting attenuation required is 8db or a gain value of 0.1585. the linear equation for calculating the gain is: gain =(level/threshold) ratio *(threshold/level) ? state transitions: in addition to calculati ng the new gain for the compressor, the gain calcu- lation block will also select the filter coeffi cient for the attack/releas e filter. the rules for selecting the coefficient are as follows: in the compression region: ? if the gain calculated is less than the last gain calculat ed (more compression is being applied), then the filter coeffi cient is the compressor attack. ? if the gain calculated is more than the last ga in calculated (less compression), the filter coef- ficient is the compressor release. ? in the expansion region: ? if the calculated gain is less than the last gain calculated (closing expander, the filter coeffi- cient is the expander attack. ? if the calculated gain is more than the last gain calculated, the filt er coefficient is the expander release. in the linear region: ? modify gain until a gain of 1.0 is obtained. ? if the last non-linear state was compression, use the compressor release. ? if the last non-linear state was ex pansion, use the expander attack. 3. attack/release filter: in order to prevent objectionable artifacts, the gain is smoothly ramped from the current value to the new value calculated by the gain calculation block. in the pc-based comp/limiter, this is achieved using a simple tra cking lowpass filter to smooth out the abrupt tran- sitions. the calculation (using the coefficient (coeff) selected by the gain block) is: filtered_gain = coeff*last_filtered_gain + (1.0 - coeff)*target_gain; this creates a exponential ramp from the current gain value to the new value.
idt confidential 17 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.7.4. limiter/compressor registers ? general compressor/limiter/expander control ? compressor/limiter/expander make-up gain ? compressor threshold ? compressor ratio register ? compressor attack time constant register (low) register address bit label type default description r37 (25h) clectl 7:5 rsvd r 0h reserved 4 lvl_mode rw 0 cle level detection mode 0 = average 1 = peak 3 windowsel rw 0 window width selection for level detection: 0 = equivalent of 512 samples of selected base rate (~10-16ms) 1 = equivalent of 64 samples of selected base rate (~1.3-2ms) 2 exp_en rw 0 1 = enable expander 1 limit_en rw 0 1 = enable limiter 0 comp_en rw 0 1 = enable compressor table 15. clectl register register address bit label type default description r38 (26h) mugain 7:5 rsvd r 0h reserved 4:0 clemug[4:0] rw 0h 0db..46.5db in 1.5db steps table 16. mugain register register address bit label type default description r39 (27h) compth 7:0 compth[7:0] rw 00h ffh..00h = 0db..95.625db in 0.375db steps. table 17. compth register register address bit label type default description r40 (28h) cmprat 7:5 rsvd r 000 reserved 4:0 cmprat[4:0] rw 00h compressor ratio 00h = reserved 01h = 1.5:1 02h..14h = 2:1..20:1 15h..1fh = reserved table 18. cmprat register register address bit label type default description r41 (29h) catktcl 7:0 catktc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a compressor attack phase. table 19. catktcl register
idt confidential 18 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier ? compressor attack time constant register (high) ? compressor release time constant register (low) ? compressor release time constant register (high) ? limiter threshold register ? limiter target register ? limiter attack time constant register (low ) ? limiter attack time constant register (high ) ? limiter release time constant register (low ) register address bit label type default description r42 (2ah) catktch 7:0 catktc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a compressor attack phase. table 20. catktch register register address bit label type default description r43 (2bh) creltcl 7:0 creltc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a compressor release phase. table 21. creltcl register register address bit label type default description r44 (2ch) creltch 7:0 creltc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a compressor release phase. table 22. creltch register register address bit label type default description r45 (2dh) limth 7:0 limth[7:0] rw 00h ffh..00h = 0db..95.625db in 0.375db steps. table 23. limth register register address bit label type default description r46 (2eh) limtgt 7:0 limtgt[7:0] rw 00h ffh..00h = 0db..95.625db in 0.375db steps. table 24. limtgt register register address bit label type default description r47 (2fh) latktcl 7:0 latktc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a limiter attack phase. table 25. latktcl register register address bit label type default description r48 (30h) latktch 7:0 latktc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a limiter attack phase. table 26. latktch register register address bit label type default description r49 (31h) lreltcl 7:0 lreltc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a limiter release phase. table 27. lreltcl register
idt confidential 19 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier ? limiter release time co nstant register (high ) 3.7.5. expander registers ? expander threshold register ? expander ratio register ? expander attack time constant register (low) ? expander attack time constant register (high) ? expander release time constant register (low) ? expander release time constant register (high) register address bit label type default description r50 (32h) lreltch 7:0 lreltc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a limiter release phase. table 28. lreltch register register address bit label type default description r51 (33h) expth 7:0 expth[7:0] rw 00h expander threshold: 0..95.625 db in 0.375db steps table 29. expth register register address bit label type default description r52 (34h) exprat 7:3 rsvd r 00h reserved exprat[2:0] rw 000 expander ratio 0h..1h = reserved 2h..7h = 1:2..1:7 table 30. exprat register register address bit label type default description r53 (35h) xatktcl 7:0 xatktc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a expander attack phase. table 31. xatktcl register register address bit label type default description r54 (36h) xatktch 7:0 xatktc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a expander attack phase. table 32. xatktch register register address bit label type default description r55 (37h) xreltcl 7:0 xreltc[7:0] rw 0 low byte of the time constant used to ramp to a new gain value during a expander release phase. table 33. xreltcl register register address bit label type default description r56 (38h) xreltch 7:0 xreltc[15:8] rw 0 high byte of the time constant used to ramp to a new gain value during a expander release phase. table 34. xreltch register
idt confidential 20 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.8. output effects the acs32201 offers bass enhancement, treble enhancement, stereo depth enhancement. the output effects pro- cessing is outlined in t he following sections.l 3.9. stereo depth (3-d) enhancement the acs32201 has a digital depth enhancement option to arti ficially increase the separation between the left and right channels, by enabling the attenuation of the content common to both channels. the amount of attenuation is program- mable within a range. the input is prescaled (f ixed) before summation to prevent saturation. the 3-d enhancement algorithm is a tried an d true algorithm that uses two principles. 1. if the material common to the two channels is removed, then the speakers will sound more 3-d. 2. if the material for the opposite ch annel is presented to the current chan nel inverted, it will tend to cancel any material from the opposite channel on the current ear. for example, if the material from the right is presented to the left ear inverted, it will cancel some of the material from the right ear that is leaking into the right ear. figure 9. 3-d channel inversion note: 3d_mix specifies the amount of the common si gnal that is subtracted from the left and right channels. this number is a fractional amount between 0 and 1. for proper operation, this value is typically negative. register address bit label type default description r57 (39h) fxctl 7:5 rsvd r 000 reserved 43denrw0 3d enhancement enable 0 = disabled 1 = enabled 3 teen rw 0 treble enhancement enable 0 = disabled 1 = enabled 2 tnlfbyp rw 0 treble non-linear function bypass: 0 = enabled 1 = bypassed 1 been rw 0 bass enhancement enable 0 = disabled 1 = enabled 0 bnlfbyp rw 0 bass non-linear function bypass: 0 = enabled 1 = bypassed table 35. fx control register left left right right
idt confidential 21 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.10. psychoacoustic bass enhancement one of the primary aud io quality issues with small spea ker systems is their inability to reproduce signif icant amounts of energy in the bass region (below 200hz). while there is no magic mechanism to make a speaker reproduce frequen- cies that it is not capable of, there ar e mechanisms for fooling the ear into thin king that the bass material is being heard. the psychoacoustic bass processor relies on a psychoacoustic principle called ?missing fundamental?. if the human ear hears a proper series of harmonics for a particular bass note, the listener will hear the fundamental of that series, even if it is not present. a processing algorithm using this principle allows for impr oving the apparent low frequency response of an audio sys- tem below what it is actually capa ble of. below is a diagram of the implementation of this algorithm. . figure 10. bass enhancement this implementation is composed of 5 major components: 1. extract filter ? this filter extracts the bass informatio n that the speaker s ystem can't reproduce. this is a 4th order band pass filter with a typical bandwidth of 1.5 to 2 octaves. 2. nlf ? this is a nonlinear function that is used to generate the harmonics of the fundamentals in the extracted audio. more on this function later. 3. limit filter ? this filter will limit the amplitude of the harmonics gen erated to prev ent the har- monics from creating noise in the midrange. too ma ny harmonics will spill into the mid range and be heard as unwanted buzzing. too few and th e psychoacoustic effect is not reached. the exact composition of this filter is still or be determined. a 2nd order filter is cu rrently sufficient for the nlf function employed. 4. mixing ? this structure allows mixing of the g enerated harmonics and the original material. 5. cutoff filter ? this filter is used to re move all material below the cutoff frequency of the speaker systems. this includes the fundamentals used to create the psychoacoustic effect, since they can't be reproduced. this is a 2nd order high pass filter. 3.10.1. non-linear function a new, more pleasing, non-linear function has been found. in particular, the new non-linear function involves two sepa- rate operations: taking the sine of the input signal, whic h generates odd harmonics, half wave rectifying the signal, which generates even harmonics. the transfer function is shown below: // sine part temp = in*mix1; // mix 1 can be between 0 and 8.0 temp = clip(temp); // clip this result to between -1 and 1 nlf extract filter limit filter cutoff filter
idt confidential 22 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier sineout = sin(temp*pi/2); // take the sine of this, the pi/2 provides full usage. // half wave rectifier part temp = in*mix2; // mix 2 can be between 0 and 8.0 temp = clip(temp); // clip this result halfout = rect(in); //half wave rectify input; // if input<0; output=0; else output=input output = sineout + halfout; // sum the two implementation notes: it is probably not practical to actua lly implement a sine function in hardware, so a table imple- mentation is probably appropriate. after some experimentatio n, a table of 512 entries provides sufficient resolution. note that the table is symmetric, sin(x) = y; sin(-x) = -y. depending on complexity of dealing with the sine, this can cut the table size in half. 3.10.2. signal processing summary ? dsp requirements: ? filters: ? extract filter - 2 biquads - 4th order extraction provides a tighter bass. ? limit filter - 1 biquad - 2nd order is now acceptable for limiting the output ? cutoff filter - 1 biquad - 2nd order is sufficient for this high pass filter. ? non-linear function: ? 2 clipping multiplies. ? sine lookup ? half wave rectifier. ?sum ?final mixer: ? 2 multplies and sum 3.10.3. control points ? bass extract filter ? controls the frequency content that is processed by the harmonic genera- tor. this is 2 biquadratic filters the 2 sets of 5 coefficients are held in the eq ram block (see eq section for ram access information and coefficient addresses). ? nonlinear function ? controls the harmonics generated. the 2 sets of coefficients are held in the eq ram block (see eq section for ram ac cess information and coefficient addresses). ? limit filter ? limits the harmonics mixed into the audio st ream. this is a biquadratic filter. the 5 coefficients are held in the eq ram block (s ee eq section for ram access information and coefficient addresses). ? cutoff filter ? limits the low frequencies sent to the speaker. this is a biquadratic filter. the 5 coefficients are held in the eq ram block (s ee eq section for ram access information and coefficient addresses). ? bass mix control ? controls the amount of the generated harmonics that are added to the orig- inal signal.
idt confidential 23 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.11. treble enhancement one of the mechanisms used to limit the bit rate for compre ssed audio is to first remove high frequency information before compression. when these files are decompressed, this can lead to dull sounding audio. the idt treble enhancement replaces these lost high frequencies. the enhanced treble function works much like the enhanced bass, however it's intended use is different. the enhanced treble uses a non linear function to add treble harmonics to a signal that has limited high-frequency bandwidth (such as a low bit rate mp3). in this case, the algorithm makes use of the audio fact that presence of audio between 4-8k is a good predictor of audio between 10k-20k. figure 11. treble enhancement this implementation extracts the high frequency content that is available in the audio, generates harmonics of those frequencies. these harmonics are then summed back into the original signal, providing a brighter sound. this algorithm has 4 components. ? extract filter ? this filter is used to extract the treble between 4-8k. this is 2 2nd order high pass filters. ? enhanced treble non-linear function ? generates high frequency components ? limit filter ? this filter limits the harmonics generated by the nlf to prevent any significant aliasing. a second order filter is sufficient. ? mixing network ? this simply sums the generated harm onic signals into the original signal. 3.11.1. enhanced treble nlf the enhanced treble nlf has a different set of requirements than the psychoacoustic bass. in par- ticular, the presence of odd high frequency harmo nics is objectionable. thus the most promising nlf for enhanced treble is a half wave rectifier. 3.11.2. signal processing summary thus the signal processing summary for the enhanced treble is currently: ? 1 bi-quad as an extraction filter. ? same as psychoacoustic bass (if possible) to a half wave rectifier - 1 comparison ? 1 bi-quad as a limit filter ? mixing network - 2 multiplies and sum. nlf extract filter limit filter
idt confidential 24 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.11.3. control points ? extract filter ? this controls which frequencies in the original material are used to create the harmonics. this is 2 biquadratic f ilters. the 2 sets of 5 coefficient s are held in the eq ram block (see eq section for ram access information and coefficient addresses.) ? nonlinear function ? this controls the creation of the ha rmonics. the 2 coefficients are held in the eq ram block (see eq section for ram ac cess information and coefficient addresses.) ? limit filter ? this limits the harmonics mixed with the audi o signal to prevent aliasing. this is a biquadratic filter. the 5 coefficients are held in the eq ram block (see eq section for ram access information and coefficient addresses.) ? treble (harmonic) mix ? controls how much of the gener ated harmonics are mixed back into the original content. 3.12. mute and de-emphasis the acs32201 has a soft mute function, which is used to gr adually attenuate the digital signal volume to zero. the gain returns to its previous sett ing if the soft mute is removed. at startup, the codec is muted by default; to enable audio play, the mute bit must be cleared to 0. after the equalization filters, de-emphasis may be performe d on the audio data to compensate for pre-emphasis that may be included in the audio stream. de-emphasis filteri ng is only available for 48khz, 44.1khz, and 32khz sample rates. 3.13. mono operation and phase inversion normal stereo operation converts left and right channel digi tal audio data to analog in separate dacs. however, it is also possible to have the same signal (left or right) app ear on both output channels by disabling one channel; alter- nately, there is a mono-mix mode that mixes the two channels di gitally before converting to using only one converter. in this mode, the resulting mixed stream signal can appear on both pwm output channels. the dac output defaults to non-inverted. setting dacpol l and dacpolr bits will invert the dac out put phase on the left and right channels. 3.13.1. dac control register register address bit label type default description r24 (18h) cnvrtr1 7 dacpolr rw 0 invert dac right signal 6 dacpoll rw 0 invert dac left signal 5:4 dmonomix [1:0] rw 00 dac mono mix 00: stereo 01: mono ((l/2)+(r/2)) into dacl, ?0? into dacr 10: mono ((l/2)+(r/2)) into dacr, ?0? into dacl 11: mono ((l/2)+(r/2)) into dacl and dacr 3dacmurw1 digital soft mute 1 = mute 0 = no mute (signal active) 2 deemp rw 0 de-emphasis enable 1 = de-emphasis enabled 0 = no de-emphasis 1:0 rsvd r 00 reserved table 36. cnvrtr1 register
idt confidential 25 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.14. analog outputs 3.14.1. speaker outputs the lspkout (l+, l-) and rspkout (r+, r-) pins are inte nded to drive an 8 ohm speaker pair. the spkout pins can drive a 16 or 32 headphone or alternately drive a line output. the signal volume of the speaker amplifier can be independently adjusted under software control by writing to spkvol_l and spkvol_r. setting the volume to 0 000000 will mute the output driver; the output remains at ground, so that no click noise is produced when muting or un-muting. gains above 0db run the risk of clipping large signals. to minimize artifacts such as clicks and zipper noise, the btl outputs feature a volume fade function that smoothly changes volume from the current value to the target value. 3.14.1.1. speaker volume control registers 3.14.2. class d audio processing the class d pwm controller performs the following signal processing: ? feedback filters are applied to shape any noise. the filters move noise from audible frequencies to frequencies above the audio range. ? the pwm block converts the data streams to tri-state pwm signals and sends them to the power stages. ? finally, the class-d controller bl ock adjusts the output volume to provide constant output power across supply voltage. the power stages boost the signals to higher levels, sufficient to drive speakers at a comfortable lis- tening level. register address bit label type default description r2 (2h) spkvoll 7 rsvd r 0 reserved 6:0 spkvol_l [6:0] rw 1101111 (0db) left speaker volume 1111111 = +12db 1111110 = +11.25db ? 1101111 = 0db ... 0001000 to 0000001 = -77.25db 0000000= mute note: if spkvolu is set, this setting will take effect after the next write to the right input volume register. r3 (3h) spkvolr 7 rsvd r 0 reserved 6:0 spkvol_r [6:0] rw 1101111 (0db) right speaker volume 1111111 = +12db 1111110 = +11.25db ? 1101111 = 0db ... 0001000 to 0000001 = -77.25db 0000000 = mute table 37. spkvol l/r registers
idt confidential 26 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.14.2.1. constant output power mode in normal operation the btl amplifier is rated at 0. 5w (full scale digital with 6db btl gain) into an 8 ohm load at 3.6v but will vary from about 0.38w to about 1.2w across a 3.1v to 5.5v supply range. however, when constant output power mode is enab led, the full scale output is held constant from 3.1v to 5.5v. the btl amplifier in acs32201 will co ntinuously adjust to power supp ly changes to en sure that the full scale output power remains constant. this is no t an automatic level control. rather, this function prevents sudden volume changes when switching between battery and line power. please note, when in this mode the amplifier efficiency may be reduced and decr eases with higher supply volt- ages and lower target values. a simple 5-bit adc is used to mo nitor pvdd. as pvdd raises or lowers, the analog circuit will send a 5-bit code to the digital section that will aver age and then calculate a gain adjustment. the btl audio signal will be multiplied by this gain valu e (in addition to the user volume controls). the user will select a target val ue for the circuit. the constant ou tput function will calculate a gain adjustment that will provide approximately the same full sc ale output voltage as provided when pvdd causes the same code value. so, if the tar get is 9 then a pvdd voltage of about 3.7v would generate a code value of 9 and a full scale output power of about 630mw into 8 ohms. if pvdd should rise to 4v, generating a code of 13, then th e constant output power circuit would reduce the gain by 0.75db (4 codes * 0.1875db) to keep the full scale output at the target level. the circuit may be configured to add gain, attenuatio n, or both to maintain the full-scale output level. if the needed adjustment falls outside of the range of the circuit (only attenuation is enabled and gain is needed, for example) then the ci rcuit will apply as much correction as it is able. through the use of gain, attenuation, and target values, different behaviors may be implemented: ? attenuation only, target set to mimic a low supply voltage - constant output level across bat- tery state with constant quality (thd/snr) ? attenuation only, target set to mimic a moderate supply voltage - output limiting to an approximate power level. leve l will decrease at lo wer supply voltages but won?t increase beyond a specific point. ? gain only, target at or near max - output will remain relative ly constant but distortion will increase as pvdd is lowered. this mimics the behavior of comm on class-ab amplifiers. ? gain and attenuation - output remains at a le vel below the maximum possible at the highest supply voltage and above the theoretical full scale at minimum supply. full scale pcm input clips when the supply voltage is low but won?t become too loud when the supply voltage is high. in addition to maintaining a constant output level, pvdd may be monitored for a large, sudden, change. if the high delta function is enabled a nd pvdd changes more than 4 code steps since the last cycle, the output will be rapidly reduced th en gradually increased to the target level. when using this circuit, please take note of the following: ? the full scale output power may be limited by the supply voltage. ? full scale output power is affected by other gain controls in the output path including the eq and compressor/limiter. ? the constant output power function is intended to help maintain a consta nt output level, not an exact output level. the output level for a specif ic target may vary part to part. if limiting is
idt confidential 27 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier required for safety or other reasons, be cons ervative and set the target well below the maxi- mum allowable level. ? noise on the pvdd supply may cause erratic behavior. use the recommended supply decoupling caps and verify that the power su pply can support the peak currents demanded by a class-d amplifier. constant output power error (db) relative to a target of 8 for an ideal part and the output error if left uncorrected across a 3.1 to 5.5v supply range. figure 12. constant output power error constant output power for nominal and high/low reference across a 3.1 to 5.5v supply range.(uncorrected power shown for reference) a ta rget of 8 roughly corres ponds to 0.5w at 3.6v into 8 ohms. \ 3 \ 2 \ 1 0 1 2 3 3.1 4.1 5.1 relative ? to ? target nom ? db
idt confidential 28 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier figure 13. constant output power nominal and high/low 3.14.2.2. under voltage lock out when the pvdd supply becomes low, the btl amplif ier may be disabled to help prevent undesir- able amplifier operation (ove rheat) or system level problems (battery under-voltage.) the same circuit that monitors the pvdd supply to help maintain a constant output power is used to monitor the pvdd supply for a critical under-voltage si tuation. if the sense circuit consistently returns a 0 code then the pvdd supply is less than the minimum required for proper operation. to prevent accidental shutdown due to a noisy supply at th e minimum operating range, the output of the pvdd sense circuit will be averaged for at least 200ms. 3.14.2.3. registers ? constant output power 1 register address bit label type default description r34 (22h) constant output power 1 7 copatten rw 0 1 = constant output powe r function will use attenuate the btl output if the pvdd sense circuit returns a code higher than the target value. 6copgainrw0 1 = constant output powe r function will use attenuate the btl output if the pvdd sense circuit returns a code higher than the target value. 5 hdeltaen rw 0 1 = if the pvdd code value has changed more than 4 counts since the last gain ad justment, the output will be reduced rapidly then slowly returned to the target level. 4:0 coptarget[4:0] rw 8h 5-bit target fo r the constant out put power function. table 38. constant output power 1 register 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 3.1 4.1 5.1 off nom hi low
idt confidential 29 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier ? constant output power 2 ? constant output power 3 ? configuration register register address bit label type default description r35 (23h) constant output power 2 7 rsvd r 0 reserved 6 rsvd r 0 reserved 5:3 avglength[2:0] rw 000 number of sense cycles to average: 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128 2:0 monrate[2:0] rw 100 rate the pvdd supply is monitored: 000 = 0.0625ms 001 = 0.125ms 010 = 0.25ms 011 = 0.5ms 100 = 1ms 101 = 2ms 110 = 4ms 111 = 8ms table 39. constant output power 2 register register address bit label type default description r137 (89h) constant output power 3 7 highdelta r 0 1 = a high delta situation has been detected (positive code change > 4) and the constant output power function is adjusting. 6 rsvd r 0 1 = constant output powe r function will use attenuate the btl output if the pvdd sense circuit returns a code higher than the target value. 5:0 copadj r 0h amount that the constant output power function is adjusting the signal gain. value is 2s compliment with each step equal to 0.1875db. the approximate range is +/- 6db table 40. constant output power 3 register register address bit label type default description r31 (1fh) config0 7:2 rsvd r 0h reserved for future use. 1 dc_bypass rw 0 1 = bypass dc removal filter (warning dc content ca n damage btl output) 0 rsvd r 0 reserved table 41. config0 register
idt confidential 30 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier ? pwm control 0 register ? pwm control 1 register ? pwm control 2 register ? pwm control 3 register register address bit label type default description r66 (42h) pwm0 7:5 scto rw 11 class-d short circuit detect time-out 00 = 10us 01 = 100us 10 = 500us 11 = 100ms 5uvlorw1 under voltage lock out 1 = btl output disabled if pvdd sense circuit returns code 0 4 roundup rw 1 1 = roundup, 0 = truncate for quantizer 3 bfclr rw 0 1 = disable binomial filter 2 fourthorder rw 1 1 = 4th order bi nomial filter; 0 = 3rd order 1 add3_sel rw 0 1 = 24-bit noise shaper output (pre-quantizer) 0 = 8/9/10-bit quantizer output 0 quantizer_sel rw 0 table 42. pwm0 register register address bit label type default description r67 (43h) pwm1 7 rsvd r 0 reserved 6:2 dithpos[4:0] rw 0 dither position, where dither inserted after ns. 0,1,2 = dither bits 2:0 4 = dither bits 3:1 5 = dither bits 4:1 .... 19 = dither bits 19:17 1 dith_range rw 0 1 = dither -1 to +1, 0 = -3 to +3 0 dithclr rw 0 1 = disable dither table 43. pwm1 register register address bit label type default description r68 (44h) pwm2 7:2 dvalue[5:0] rw 18h dvalue constant field 1 pwm_outflip rw 0 1 = swap pwm a/b output pair for all channels the control lines to the power stage are swapped inverting the output signal. 0 pwm_outmode rw 1 1 = tristate, 0 = binary table 44. pwm2 register register address bit label type default description r69 (45h) pwm3 7:6 outctrl[1:0] rw 00 pwm output muxing 0 = normal 1 = swap 0/1 2 = ch0 on both 3 = ch1 on both 5:0 cvalue[5:0] rw 0ah tristate constant field, must be even and not 0 table 45. pwm3 register
idt confidential 31 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.15. other output capabilities each audio analog output can be separately enabled. disa bling outputs serves to reduce power consumption, and is the default state of the device. 3.15.1. audio output control see power management section. th e output enable bits are also power management bits and the outputs will be turned off when disabled. 3.15.2. speaker enable the spkr_en pin is used to enable the speaker outputs.. control bits determine the meaning and polarity of the input. register address bit label type default description r27 (1bh) power management (2) 7:5 rsvd rw 0 reserved 4 spkoutl rw 0 left speaker output enable 3 spkoutr rw 0 right speak er output enable 2 rsvd rw 0 1 rsvd rw 0 0 vref rw 1 voltage reference note : a value of ?1? indicates the output is enabled; a value of ?0? disables the output. table 46. power management 2 register
idt confidential 32 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.15.2.1. speaker enable register 3.15.3. speaker operation 3.16. thermal shutdown to avoid overpowering and ov erheating the codec when the amplifier outputs are driving large currents, the acs32201 incorporates a thermal protection circuit. if enabled, and the device temperature reaches approximately 150c, the speaker and headphone amplif ier outputs will be disabled. once the de vice cools, the outp uts will be automatically re-enabled. 3.16.1. algorithm description: there are 2 trip points, ?high? and ?low?. high indica tes a critical overheat requiring a reduction in vol- ume to avoid damage to the part. low is set for a slig htly lower temperature point, indicating that the current level is safe bu t that increased volume would result in a critic al overheat condition. normally, the overheat bits are polled every 8ms but may be polled at 4ms, 8ms, 16ms, or 32ms by adjusting the poll value. re ductions in volume will be allowed to happen at the poll rate. increases in volume are programmable to happen every 1, 2, 4, or 8 poll cycles and in steps of 0.75db to 6db. this allows a full scale volume increase in a range of 10s of milliseconds to 10s of seconds. register address bit label type default description r29 (1ch) additional control (ctl) 7swenrw0 spkr_en input 0: disabled 1: enabled 6swpolrw0 speaker polarity 0: speaker off when pin is high 1: speaker is on when pin is high 5:2 rsvd rw 00 reserved 1 tsden rw 0 thermal shutdown enable (see section 7.9) 0: thermal shutdown disabled 1: thermal shutdown enabled 0toenrw0 zero cross time-out enable 0: time-out disabled 1: time-out enabled - volumes updated if no zero cross event has occurred before time-out table 47. additional control register swen swpol spkr_en pin state spkout 1 1.spkout = logical or of the spkl and spkr enable (power state) bits speaker enabled 0xx0no 0xx1yes 1000no 1001yes 101xno 110xno 1110no 1111yes table 48. speaker operation
idt confidential 33 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier when both overheat bits are 0, the volume is allo wed to increment by the incstep size, unless the volume has already reached the maximum value allowed. any subs equent increment will be held off until the programmed number of polling cycles have occurred. when the low overheat bit is 1 and the high overheat bit is 0, this indicates that the volume is cur- rently at a safe point but the temperature is higher than desired and incrementing the volume may cause severe overheating. the volume is held at the current value. when the high overheat bit is 1, damage could occur, so the volume se tting will be immediately reduced by the decrem ent step value. as the ov erheat bits are re-polled, this volume reduction will continue until the high overheat bit drops to 0 or the volume value reaches the minimum setting. if the high overheat bit remains 1 even at the minimum setting, th en the mute control bit will be asserted. if the high ov erheat bit persists even after mute , then the btl amp will be powered down. 3.16.2. thermal trip points. the high and low trip points can be adjusted to su it the needs of a particular system implementation. there is a ?shift? value (tripshift) which sets the lo w trip point, and there is a ?split? value (tripsplit) that sets how many degrees above the low trip point the high trip point is. by default: tripshift = 2 (140 degrees c) tripsplit = 0 (15 degrees c) therefore: high trip point = 155c. low trip point = 140c.
idt confidential 34 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.16.3. temperature limit state diagram: figure 14. temp sense volume adjustment algorithm 3.16.4. instant cut mode this mode can be used to make our algorithm reac t faster to reduce the rmal output but will cause more pronounced volume changes. if enabled: ? only the high overheat is used, the low overheat is ignored. ? whenever polled, if the high over heat is 1, then the volume setting will immediately be set to 0h. ? conversely, if the high overheat is 0, the volume setting will immediately be set to the maxvol value. ? both volume clear and volume set events occur at the polling rate. during this mode, the algorithm still possesses th e ability to mute and then power down the btl amp if the high overheat continues to be 1. this mode is disabled by default. 3.16.5. short circuit protection to avoid damage to the outputs if a short circuit condition should occur, both the headphone and btl amplifiers imple- ment short circuit protection circuits. th e headphone output amplifier will detect the load current and limit its output if in an over current state. the btl amplifie r will sense a short to pvdd, ground, or between its +/- outputs and disable its output if a short is dete cted. after a brief time, the amplifier will turn on again. if a short circuit condition is still pres ent, the amplifier will disable itself again. increment ratio count overheathl ==? idle ts disabled every ?poll? time (8ms default) 01 00 1x increment volume by incstep ratio met & vol /= max? no yes vol @ min? yes no vol = mute? yes decrement volume by decstep volume = mute btl pwd no
idt confidential 35 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.16.6. thermal shutdown registers the thermal shutdown circuit is enabled using the additional control register, see table 49. 3.16.6.1. additional control register 3.16.6.2. temp sensor control/status register register address bit label type default description r29 (1ch) additional control (ctl) 7swenrw0 spkr_en input 0: disabled 1: enabled 6swpolrw0 speaker polarity 0: off 1: on 5:2 rsvd rw 00 reserved 1 tsden rw 0 thermal shutdown enable (see section 7.9) 0: thermal shutdown disabled 1: thermal shutdown enabled 0toenrw0 zero cross time-out enable 0: time-out disabled 1: time-out enabled - volumes updated if no zero cross event has occurred before time-out table 49. additional control register register address bit label type default description r29 (1dh) temp sensor control/status (thermts) 7 triphighstat r 0 temp sensor high trip point status 0 = normal operation 1 = over temp condition 6 triplowstat r 0 temp sensor low trip point status 0 = normal operation 1 = over temp condition 5:4 tripsplit[1:0] rw 0h temp sensor ?split? setting. determines how many degrees above the low trip point the high trip is set: 0h = 15 degrees c 1h = 30 degrees c 2h = 45 degrees c 3h = 60 degrees c. 3:2 tripshift[1:0] rw 2h temp sensor ?shift? setting. determines the low trip temperature: 0h = 110 degrees c 1h = 125 degrees c 2h = 140 degrees c 3h = 155 degrees c. 1:0 poll[1:0] rw 1h temp sensor polling interval 0h = 4ms 1h = 8ms 2h = 16ms 3h = 32ms table 50. thermts register
idt confidential 36 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 3.16.6.3. temp sensor status register register address bit label type default description r30 (1eh) speaker thermal algorithm control (thermspkr1) 7forcepwdrw1 force powerdown enable for the speaker thermal algorithm: 0 = speaker will remain powered up even if the temp sensor continues to report an overheat condition at minimum volu me (mute) 1 = speaker will be powered down if the temp sensor reports an overheat at the minimum volume (mute) 6 instcutmode rw 0 instant cut mode 0 = both temp sensor status bits used to smoothly adjust the volume. 1 = only the high temp sensor status bit will be used to set the volume. volume will be set to the full volume or mute (incstep and decstep are ignored.) 5:4 incratio[1:0] rw 0h increment interval ratio. determines the ratio between the speaker volume increment interval and the speaker volume decrement interval (increment rate is equal to or slower than decrement rate): 0h = 1:1 1h = 2:1 2h = 4:1 3h = 8:1 3:2 incstep[1:0] rw 0h increment step size for t he speaker thermal control algorithm (occurs at the temp sensor polling rate x the increment interval ratio.) 0h = 0.75db 1h = 1.5db 2h = 3.0db 3h = 6.0db 1:0 decstep[1:0] rw 1h decrement step size for the speaker thermal control algorithm (occurs at the temp sensor polling rate.) 0h = 3db 1h = 6db 2h = 12db 3h = 24db table 51. thermtspkr1 register register address bit label type default description r136 (88h) speaker thermal algorithm status (thermspkr2) 7 forcepwdstatus r 0 0: speaker not powered down due to thermal algorithm 1: speaker has been powered down because overtemp condition was present even though the speaker was muted. 6:0 volstatus[6:0] r 08 current speaker volume value. if no overheat is being reported by the temperature sensor, this value should be equal to the greater of the left or right speaker volume setting. table 52. thermtspkr2 register
idt confidential 37 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 4. digital audio and control interfaces 4.1. data interface for digital audio data, the acs32201 uses 3 pins to input and output digital audio data. ? dacdin: dac data input ? daclrck: dac data alignment clock ? dacbclk: bit clock, for synchronization the clock signals dacbclk and daclrck are outputs when the acs32201 operates as a master; they are inputs when it is a slave. three different data formats are supported: ? left justified ? right justified ?i 2 s all of these modes are msb first. 4.2. master and slave mode operation the acs32201 can be used as either a master or slave de vice, selected by the ms bit. when operating as a master, the acs32201 generates dacbclk and daclrclk and contro ls sequencing of the data transfer the data pins. in slave mode, the acs32201 provides da ta aligned to clocks it receives. figure 15. master mode figure 16. slave mode dacbclk daclrclk dacdin codec dsp encoder/ decoder dacbclk daclrclk dacdin codec dsp encoder/ decoder
idt confidential 38 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 4.3. audio data formats the acs32201 supports 3 common audio interface formats and programmable clocking that provides broad compati- bility with dsps, consumer audio and video socs, fpgas, handset ch ipsets, and many other products. in all modes, depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. if the co nverter word length is smaller than the num ber of clocks per sample in the frame then the dac will ignore (truncate) the extra bi ts. if the converter word l ength chosen is la rger than the number of clocks available per sample in the frame, and the dac data will be zero padded. 4.4. left justified audio interface in left justified mode, the msb is available on the first ri sing edge of bclk following a lrclk transition. the other bits are then transmitted in order. the lrclk signal is high when left channel data is present and low when right channel data is present. figure 17. left justified audio interface (assuming n-bit word length) 4.5. right justified audio interf ace (assuming n-bit word length) in right justified mode, the lsb is ava ilable on the last rising edge of bclk before a lrclk transition. all other bits are transmitted in order. the lrclk signal is high when left channel data is present and low when right channel data is present. figure 18. right justified audio interface (assuming n-bit word length) left justified bclk lrclk n sdi / sdo left channel right channel word length (wl) 1/fs n-1 n-2 3 2 1 msb lsb n n-1 n-2 3 2 1 msb lsb bclk lrclk n sdi / sdo left channel right channel word length (wl) right justified 1/fs n-1 n-2 3 2 1 msb lsb n n-1 n-2 3 2 1 msb lsb
idt confidential 39 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 4.6. i 2 s format audio interface in i 2 s mode, the msb is available on the se cond rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. figure 19. i 2 s justified audio interface (assuming n-bit word length) 4.7. data interface registers 4.7.1. audio data format control register register address bit label type default description r19 (13h) digital audio interface format (aic1) 7 rsvd r 0 reserved 6 bclkinv rw 0 bclk invert bit (for master and slave modes) 0 = bclk not inverted 1 = bclk inverted 5msrw0 master / slave mode control 1 = enable master mode 0 = enable slave mode 4lrprw0 right, left and i 2 s modes ? lrclk polarity 1 = invert lrclk polarity 0 = normal lrclk polarity 3:2 wl[1:0] rw 10 audio data word length 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 1:0 format[1:0] rw 10 audio data format select 11 = reserved 10 = i 2 s format 01 = left justified 00 = right justified table 53. aic1 register i2s bclk lrclk n sdi / sdo left channel right channel word length (wl) 1/fs n-1 n-2 3 2 1 msb lsb n n-1 n-2 3 2 1 msb lsb 1 bclk 1 bclk
idt confidential 40 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 4.7.2. audio interface output tri-state tri is used to tri-state the daclrck and dacbclk pins . in slave mode (master=0) all pins are configured as inputs. the tri-stated pins are pulled low with an internal pull-down resistor unless that resistor is disabled. 4.7.3. audio interface control 3 register 4.8. bit clock mode the default master mode bit clock gene rator automatically produces a bit clock frequency based on the sample rate and word length. when enabled by setting the appropriate bcm bits, the bit clock mode (bcm) function overrides the default master mode bit clock generator to produce the bit clock frequency shown below: note that selecting a word length of 24-bits in auto mode generates 64 clocks per frame (64fs) . the bcm mode bit clock generator produces 16, 20, or 32 bit cycles per sample. register address bit label type default description r20 (14h) audio interface control 2 (aic2) 7:6 dacdsel[1:0] rw 00 00: left dac = left i2s data; right dac = right i2s data 01: left dac = left i2s data; right dac = left i2s data 10: left dac = right i2s data; right dac = right i2s data 11: left dac = right i2s data; right dac = left i2s data 5:4 rsvd rw 00 reserved 3trirw0 tri-states daclrclk and dacbclk pins. 0 = daclrclk and dacbclk are inputs (slave mode) or outputs (master mode) 1 = daclrclk and dacbclk are high impedance 2:0 blrcm[2:0] rw 000 bitclock and lrclock mode. see table below table 54. aic2 register register address bit label type default description r21 (15h) audio interface control 3 (aic3) 7:3 rsvd r 0 reserved 2 ddipdd rw 0 dacdin pull-down disable 0 = pull-down active 1 = pull-down always disabled 1dlrpddrw0 daclrclk pull-down disable 0 = pull-down active when configured as input 1 = pull-down always disabled 0 dbcpdd rw 0 dacbclk pull-down disable 0 = pull-down active when configured as input 1 = pull-down always disabled table 55. aic3 register register address bit label type default description r25 (17h/19h dac sample rate control 7:6 dbcm[1:0] rw 00 bclk frequency 00 = auto 01 = 32 x fs 10 = 40 x fs 11 = 64 x fs table 56. master mode bclk frequency control register
idt confidential 41 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier figure 20. bit clock mode note: the clock cycles are evenly distributed throughout the frame (true multiple of lrclk not a gated clock.) 4.9. control interface the registers are accessed through a serial control interfac e using a multi-word protocol comprised of 8-bit words. the first 8 bits provide the device address and read/write flag. in a write cycle, the next 8 bits provide the register address; all subsequent words contain the data, corresponding to the 8 bits in each control register.the control interface oper- ates using a standard 2-wire interface, as a slave device only. 4.9.1. register write cycle the controller indicates the start of data transfer with a high to low transition on sda while scl remains high, signalling that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matc hes the address of the acs32201 and the r/w bit is ?0?, indicating a write, then the acs32201 responds by pulling sda low on the next clock pulse (ack); otherwise, the acs32201 returns to the idle condition to wait for a new start condition and valid address. once the acs32201 has acknowledged a correct device address, the controller sends the acs32201 register address. the acs32201 ack nowledges the register a ddress by pulling sda low for one clock pulse (ack). the controller then s ends a byte of data (b7 to b0), and the acs32201 acknowledges again by pulling sda low. when there is a low to high transition on sda while scl is high, the transfer is complete. after receiving a complete address and data sequence the acs32201 returns to the idle state. if a start or stop condition is detected out of sequence, the device returns to the idle condition. figure 21. 2-wire serial control interface the acs32201 has device address d4. fs x 64 fs x 40 lrclk fs x 32 nw scl sda device address da[6:0] start ack register address ra[7:0] register data rd[7:0] ack ack stop
idt confidential 42 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 4.9.2. multiple write cycle the controller may write more than one register within a single write cycle. to write additional regis- ters, the controller will not generate a stop or star t (repeated start) command after receiving the acknowledge for the second byte of information (register address and data). instead the controller will continue to send bytes of data. after each byte of data is receiv ed, the register address is incre- mented. figure 22. multiple write cycle 4.9.3. register read cycle the controller indicates the start of data transfer with a high to low transition on sda while scl remains high, signalling that a device address and data will follow. if the device address received matches the address of the acs32201 and the r/w bit is ?0?, indicating a wr ite, then the acs32201 responds by pulling sda low on the next clock puls e (ack); otherwis e, the acs32201 returns to the idle condition to wait for a new start condition and valid address. once the acs32201 has acknowledged a correct a ddress, the controller sends a restart command (high to low transition on sda wh ile scl remains high). the controller then re-sends the devices address with the r/w bit set to ?1? to indicate a read cycle.the acs32201 acknowledges by pulling sda low for one clock pulse. the controller then receives a byte of register data (b7 to b0). for a single byte transfer, the ho st controller will not acknowledge (h igh on data line) the data byte and generate a low to high transition on sda while scl is high, completing the transfer. if a start or stop condition is detected out of sequence, the device returns to the idle condition. figure 23. read cycle the acs32201 has device address d4. 4.9.4. multiple read cycle the controller may read more than one register within a single read cycle. to read additional registers, the controller will not generate a stop or star t (repeated start) command after sending t he acknowledge for the byte of data. instead the controller will continue to provide cl ocks and acknowledge after each byte of received data. the codec will automat- ically increment the internal register address after each register has had its data successfully read (ack from host) but will not increment the register a ddress if the data is not rece ived correctly by the host (n ack from host) or if the bus cycle is terminated unexpectedly (however the eq/filter addre ss will be incremented even if the register address is not incremented when performing eq/filter ram reads). by automa tically incrementing the internal register address after each byte is read, all the internal registers of the codec may be read in a single read cycle. nw scl sda device address da[6:0] start ack register address ra[7:0] register data rd[7:0] ack ack stop ack ack register write 1 register write 2 ... register data rd[7:0] @ra[7:0]+1 register write n register data rd[7:0] @ra[7:0]+n nack scl sda device address da[6:0] nw start ack register address ra[7:0] register data rd[7:0] ack stop device address da[6:0] r ack restart
idt confidential 43 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier figure 24. multiple read cycle 4.9.5. device addressing and identification the acs32201 has a default slave ad dress of d4. however, it is so metimes necessary to use a dif- ferent address. the acs32201 has a device address r egister for this purpose. the part itself has an 8-bit identification register and an 8-bit revision r egister that provide device specific information for software. in addition, an 8-bit programmable subsystem id register can allow firmware to provide a descriptive code to higher level software such as an operating system driver or application software. 4.9.5.1. device registers ? device address register ? device identification registers ? device revision register 4.9.5.2. register reset the acs32201 registers may be reset to their defau lt values using the reset register. writing a spe- cial, non-zero value to this register causes all ot her registers to assume their default states. device status bits will not necessarily change their va lues depending on the state of the device. register address bit label type default description r124 (7ch) devadr 7:1 addr[7:1] rw 1101010 7-bit slave address 0 rsvd r 0 not used - this bit is the r/nw bit in the 2-wire protocol. table 57. devadrl register register address bit label type default description r126 (7eh) devidh 7:0 did[15:8] r 32h 16-bit device identification number. contact idt. r125 (7dh) devidl 7:0 did[7:0] r 01h table 58. devid h&l registers register address bit label type default description r127 (7fh) revid 7:4 maj[3:0] r xh 4-bit major revision number. contact idt. 3:0 mnr[3:0] r xh 4-bit minor revision number. contact idt. table 59. revid register register address bit label type default description r128 (80h) reset 7:0 reset[7:0] rw 00h reset register writing a value of 85h will cause registers to assume their default values. reading this register returns 00h table 60. reset register da[6:0] nw ack ra[7:0] rd[7:0] ack ack nack da[6:0] r ack sr s p set register address read register @ ra[7:0] rd[7:0] read register @ ra[7:0] + 1 ack rd[7:0] read register @ ra[7:0] + n
idt confidential 44 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 5. audio clock generation 5.1. internal clock generation the pll block provides two clocks for t he audio portion of the device. they are ? 122.880 mhz (2560 x 48 khz) ? 112.896 (2560 x 44.1 khz) it is important that the crystal os cillator and needed plls remain on until all audio functions are dis- abled. 5.2. clocking and sample rates the acs32201 utilizes internal plls to generate the audio mast er clock (mclk) at 56.44 8mhz (22.5792mhz *2.5) and 61.44mhz (24.576 *2.5). it then generates audio sample rates directly from the master clock. after changing rate, a delay of up to 5ms may be needed for the part to properly lock plls, flush filters, etc . the clocking of the acs32201 is controlled using the br[1:0] and bm [2:0] control bits. each value of br[1:0] + bm[2:0]selects one combination of mc lk division ratios and hence one combination of sample rates the br[1:0] and bm[2:0] bits must be set to configure the appropriate adc and dac sample rates in both master and slave mode. register address bit label type default description r25 (19h) dac sample rate control (dacsr) 7:6 dbcm[1:0] rw 00 dac bit clock mode (for data interface dacbclk generation in master mode) 00 = auto 01 = 32x fs 10 = 40x fs 11 = 64x fs 5 rsvd r 0 reserved 4:3 dbr[1:0] rw 10 dac base rate 00 = 32khz 01 = 44.1khz 10 = 48khz 11 = reserved 2:0 dbm[2:0] rw 010 dac base rate multiplier 000 = 0.25x 001 = 0.50x 010 = 1x 011 = 2x 100-111 = reserved table 61. dacsr register br [1:0] bm [2:0] mclk sample rate 00 000 40.96 mhz 8 khz (mclk/5120) 001 16 khz (mclk/2560) 010 32 khz (mclk/1280) 011 reserved 100-111 reserved table 62. master clock and sample rates
idt confidential 45 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 01 000 56.448 mhz 11.025 khz (mclk/5120) 001 22.05 khz (mclk/2560) 010 44.1 khz (mclk/1280) 011 88.2 khz (mclk/640) 100-111 reserved 10 000 61.44 mhz 12 khz (mclk/5120) 001 24 khz (mclk/2560) 010 48 khz (mclk/1280) 011 96 khz (mclk/640) 100-111 reserved 11 000-111 - reserved br [1:0] bm [2:0] mclk sample rate table 62. master clock and sample rates
46 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 6. characteristics 6.1. electrical specifications 6.1.1. absolute maximum ratings stresses above the ratings listed below can caus e permanent damage to the acs32201. these rat- ings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other condi tions above those indicated in the operational sec- tions of the specifications is not implied. expo sure to absolute maximu m rating conditions for extended periods can affect pro duct reliability. electrical parame ters are gua ranteed only over the recommended operating temperature range. 6.1.2. recommended operating conditions item maximum rating voltage on any pin relative to ground vss - 0.3v to vdd + 0.3v operating temperature 0 o c to 70 o c storage temperature -55 o c to +125 o c soldering temperature 260 o c micbias output current 3ma amplifier maximum supply voltage 6 volts = pvdd audio maximum supply voltage 3 volts = avdd/cpvdd digital i/o maximum supply voltage 3.6 volts = dvdd_io digital core maximum supply voltage 2.0 volts = dvdd table 63. electrical speci fication: maximum ratings parameter min. typ. max. units power supplies dvdd_core 1.4 2.0 v dvdd_io 1.4 3.5 avdd/cpvdd 1.7 2.0 pvdd 3.0 5.5 v ambient operating temperature analog - 5 v 0 25 70 o c case temperature t case 90 o c table 64. recommended operating conditions esd: the acs32201 is an esd (electrostatic discharge) sens itive device. the human body and test equipment can accumulate and discharge electrostatic charges up to 4000 volts without detection. even t hough the acs32201 implements internal esd protection circuitry, proper esd precautions sh ould be followed to avoid damaging the functionality or performance.
47 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 6.2. device characteristics (t ambient = 25 oc, dvdd_core=dvdd_io=avdd=1.9v, pvdd=3.6v, 997hz signal, fs=48khz, input gain=0db, 24-bit audio ) parameter symbol test conditions min typ max unit speaker outputs (l+, l-, r+, r- with 8ohms bridge-tied load) full scale output level v fsov pvdd=5v pvdd=3.6v 3.0 2.1 vrms output power p o 997hz full scale signal, output power mode disabled pvdd=5v, 8ohm pvdd=3.6v, 8ohm 1 0.5 w(ave) pvdd = 5v, 4 ohm didd = 3.6v, 4 ohm 2 1 w(ave) signal to noise ratio snr a-weighted 90 db total harmonic distortion + noise thd+n 5v/8ohms/0.5w 0.05 % speaker supply leakage current i pvdd 1ua efficiency h pvdd=3.6v rl=8,p o = 0.5w pvdd=5v rl=8,p o = 1w pvdd=3.6v rl=4,p o = 1w pvdd=5v rl=4,p o = 2w 87 87 83 83 % analog voltage reference levels charge pump output v- -5% -avdd +100mv +5% v digital input/output adc/dac bclk input rate fmax 30 mhz i2s bclk/lrclk ratio 32 1022 clocks/ frame input high level v ih 0.7x dvdd_ io v input low level v il 0.3x dvdd_io v output high level v oh i oh =-1ma 0.9x dvdd_io v output low level v ol i ol =1ma 0.1xdvdd_io v input capacitance 5pf input leakage -0.9 0.9 ua esd / latchup iec1000-4-2 1 level jesd22-a114-b 2 class jesd22-c101 4 class table 65. device characteristics
idt confidential 48 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 6.3. typical power consumption 6.4. low power mode power consumption table 67. low power mode power consumption low power settings 1) dac/adc modulators set to half rate 2) constant output power function disabled 3) all unused functions disabled (for example, input pga, input mux, and adc disabled for playback tests) 4) register 0x73=0x06 5) register 0x75=0x02 6) pll block power consumption not included mode avdd (v) pvdd (v) dvdd_io dvdd_core (v) i avdd (ma) i pvdd (ma) i dvdd_i o (ma) i dvdd_co re (ma) p total (mw) notes playback to speaker only 1.9 3.6 1.9 <1 329 2 9 1206 full scale 500mw/8ohms; includes load but not pll/clock buffer section. fs=48khz, stereo. table 66. typical power consumption mode avdd (v) pvdd (v) dvdd_io dvdd_core (v) i avdd (ma) i pvdd (ma) i dvdd_i o (ma) i dvdd_co re (ma) p total (mw) notes playback to speaker only 1.9 3.6 1.9 <1 336 2 7 1228 500mw/8ohms; includes load but not pll/clock buffer section. fs=48khz, stereo.
idt confidential 49 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 7. register map register (d15:9) name remarks bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] default r0 (00h) rsvd reserved 77h r1 (01h) rsvd reserved 77h r2 (02h) spkvoll spkr left volume spkvol_l[6:0] 6fh r3 (03h) spkvolr spkr right volume spkvol_r[6:0] 6fh r4 (04h) dacvoll left dac volume dacvol_l[7:0] ffh r5 (05h) dacvolr right dac volume dacvol_r[7:0] ffh r6 (06h) rsvd reserved bfh r7 (07h) rsvd reserved bfh r8 (08h) rsvd reserved 17h r9 (09h) rsvd reserved 17h r10 (0ah) vuctl volume update control dacfade dacvolu spkvolu c0h r11 (0bh) rsvd reserved 00h r12 (0ch) rsvd reserved 00h r13 (0dh) rsvd reserved 00h r14 (0eh) rsvd reserved 00h r15 (0fh) rsvd reserved 7bh r16 (10h) rsvd reserved 00h r17 (11h) rsvd reserved 32h r18 (12h) rsvd reserved 00h r19 (13h) aic1 audio interface 1 bclkinv ms lrp wl[1:0] format[1:0] 0ah r20 (14h) aic2 audio interface 2 dacdsel[1:0] tri blrcm[2:0] 00h r21 (15h) aic3 audio interface 3 ddipdd dlrpdd dbcpdd 00h r22 (16h) rsvd reserved 08h r23 (17h) rsvd reserved 12h r24 (18h) cnvrtr1 dac control dacpolr dacpoll dmonomix[1:0] dacmu deemph 08h r25 (19h) dacsr dac sample rate dbcm[1:0] dbr[1:0] dbm[2:0] 12h r26 (1ah) pwrm1 pwr mgmt (1) digenb 00h r27 (1bh) pwrm2 pwr mgmt (2) spkl spkr vref 00h r28 (1ch) ctl additional control swen swpol tsden toen 00h r29 (1dh) thermts temp sensor control triphighstat triplowstat tripsplit[1:0] tripshift[1:0] poll[1:0] 09h r30 (1eh) thermspkr1 speaker thermal algorithm control forcepwd instcutmod e incratio[1:0] incstep[1:0] decstep[1:0] 81h r31 (1fh) config0 config0 dsdm1 dsdm0 dc_bypass sd_force_on a0h r32 (20h) config1 config1 eq2_en eq2_be2 eq2_be1 eq2_be0 eq1_en eq1_be2 eq1_be1 eq1_be0 00h r33 (21h) gainctl gain control zerodet_flag zerodetlen1 zerodetlen0 auto_mute 24h r34 (22h) cop1 constant output power1 copatten copgain hdeltaen coptarget[4:0] 08h r35 (23h) cop2 constant output power2 hdcomp mode avglength[3:0] monrate[1:0] 02h r36 (24h) rsvd reserved 00h r37 (25h) clectl cmplmtctl lvl_mode windowsel exp_en limit_en comp_en 00h r38 (26h) mugain clemakeupgain clemug 4 clemug3 clemug2 clemug1 clemug0 00h r39 (27h) compth compressor threshold compth7 compth6 compth5 compth4 compth3 compth2 compth1 compth0 00h r40 (28h) cmprat compressor ratio cmprat4 cmprat3 cmprat2 cmprat1 cmprat0 00h r41 (29h) catktcl comp attack time const low catktc7 catktc6 catktc5 catktc4 catktc3 catktc2 catktc1 catktc0 00h r42(2ah) catktch comp attack time const high catktc15 catktc14 catktc13 catktc12 catktc11 catktc10 catktc9 catktc8 00h r43 (2bh) creltcl comp release time const low creltc7 creltc6 creltc5 creltc4 creltc3 creltc2 creltc1 creltc0 00h r44 (2ch) creltch comp release time const high creltc15 creltc14 creltc13 creltc12 creltc11 creltc10 creltc9 creltc8 00h r45 (2dh) limth limiter threshold limth7 limth 6 limth5 limth4 limth3 limth2 limth1 limth0 00h r46 (2eh) limtgt limiter target limtgt7 limtg6 limtgt5 limtgt4 limtgt3 limtgt2 limtgt1 limtgt0 00h r47 (2fh) latktcl limiter attack time constant low latktc7 latktc6 latktc5 latktc4 latktc3 latktc2 latktc1 latktc0 00h r48 (30h) latktch limiter attack time constant high latktc15 latktc14 latktc13 latktc12 latktc11 latktc10 latktc9 latktc8 00h r49 (31h) lreltcl limiter release time constant low lreltc7 lreltc6 lreltc5 lreltc4 lreltc3 lreltc2 lreltc1 lreltc0 00h r50 (32h) lreltch limiter release time constant high lreltc15 lreltc14 lreltc13 lreltc12 lreltc11 lreltc10 lreltc9 lreltc8 00h r51 (33h) expth expander threshold expth7 expth6 expth5 expth4 expth3 expth2 expth1 expth0 00h table 68. register map
idt confidential 50 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier note: ? registers not described in this map should be considered ?reserved?. ? numerous portions of the register map are comp atible with popular codecs from other vendors. r52 (34h) exprat expander ratio exprat2 exprat1 exprat0 00h r53 (35h) xatktcl expander attack time constant low xatktc7 xatktc6 xatktc5 xatktc4 xatktc3 xatktc2 xatktc1 xatktc0 00h r54 (36h) xatktch expander attack time constant high xatktc15 xatktc14 xatktc13 xatktc12 xatktc11 xatktc10 xatktc9 xatktc8 00h r55 (37h) xreltcl expander release time constant low xreltc7 xreltc6 xreltc5 xreltc4 xreltc3 xreltc2 xreltc1 xreltc0 00h r56 (38h) xreltch expander release time constant high xreltc15 xreltc14 xreltc13 xreltc12 xreltc11 xreltc10 xreltc9 xreltc8 00h r57 (39h) fxctl effects control 3den teen tnlfbyp been bnlfbyp 00h r58 (3ah) daccrwrl daccram_write_lo daccrwd[7:0] 00h r59 (3bh) daccrwrm daccram_write_mid daccrwd[15:8] 00h r60 (3ch) daccrwrh daccram_write_hi daccrwd[23:16] 00h r61 (3dh) daccrrdl daccram_read_lo daccrrd[7:0] 00h r62 (3eh) daccrrdm daccrram_read_mid daccrrd[15:8] 00h r63 (3fh) daccrrdh daccrram_read_hi daccrrd[23:16] 00h r64 (40h) daccraddr daccram_addr daccradd[7:0] 00h r65 (41h) dcofsel dc_coef_sel dc_coef_sel[2:0] 05h r66-123 rsvd rsvd na r124(7ch) devadr i2c device address addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 d4h r125(7dh) devidl device idlow did7 di d6 did5 did4 did3 di d2 did1 did0 32h r126(7eh) devidh device id high did15 did14 did13 did12 did11 did10 did9 did8 01h r127(7fh) revid device revision ma j3 maj2 maj1 maj0 mnr3 mnr2 mnr1 mnr0 xxh 1 r128(80h) reset reset writing 0x85 to this register resets all registers to their default state 00h r129-r135 (81h - 87h) reserved rsvd na r136(88h) thermspkr2 speaker thermal algorithm status forcepwd status volstatus[6:0] 08h r137-r255 (88h-ffh) reserved rsvd na 1. for device revision information, please contact idt. register (d15:9) name remarks bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] default table 68. register map
idt confidential 51 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 8. pin information 8.1. acs32201 tag pinout figure 25. acs32201 tag pinout class d r- class d r+ pvdd pvdd pvss pvss spkr_en class d l- class d l+ pvdd pvdd nc pvss avdd avss nc nc avss nc avdd avdd avss nc avdd nc nc nc avss vref nc nc nc nc nc nc pvss nc nc vdd_pll3 vss_pll mclk_in nc vdd_xtal i2c_scl i2c_sda nc vdd_pll1 nc nc nc nc nc nc nc nc vss_xtal dvddio dvss dvdd_core dacbclk daclrclk dacdin testa testb testc acs32201 (top view) nc vdd_pll2 test 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 68 51 49 47 45 43 41 39 37 50 48 46 44 42 40 38 36 35
idt confidential 52 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 8.2. acs32201 nag pin diagram figure 26. acs32201 nag pinout 2 3 4 5 6 7 8 9 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 28 27 26 25 24 23 22 21 20 19 avdd dvdd_core dvss daclrclk dacbclk dvddio dacdin testa mclk vss_pll vdd_xtal/pll2 testc i2c_sda vdd_pll1/3 i2c_scl classd_r- pvdd classd_r+ pvss classd_l- classd_l+ vss_xtal test spkr_en avdd avss avdd avss vref avss acs32201 5x5mm 36-pad hla top view nc testb pvdd nc nc
idt confidential 53 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 8.3. acs32201tag pin tables 8.3.1. acs32201tag power pins to ta l p i n s : 2 5 8.3.2. acs32201 tag reference pins to ta l p i n s : 1 8.3.3. acs32201 tag analog output pins to ta l p i n s : 4 pin name pin function i/o internal pull-up pull-down pin location pvdd btl supply i(power) none 40, 41, 50,51 pvss btl supply i(power) n one 44, 45, 46, 47 dvdd_core dsp and other core logic+clocks i(power) none 10 dvddio interface (i 2 s, i 2 c, gpio) i(power) none 12 dvss digital return i(power) none 11 avdd analog core supply i(power) none 4, 5, 56, 64 avss analog return i(power) none 2, 3, 57, 62 vdd_pll1 pll supply i(power) none 21 vdd_pll3 pll supply i(power) none 31 vdd_pll2 pll supply i(power) none 38 vdd_xtal oscillator supply i(power) none 36 vss_pll pll return i(power) none 32 vss_xtal oscillator return i(power) none 37 table 69. acs32201 tag power pins pin name pin function i/o internal pull-up pull-down pin location vref vref reference pin (bypass) i(analog) none 1 table 70. acs32201 tag reference pins pin name pin function i/o internal pull-up pull-down pin location class d l+ btl left positive output i(analog) none 49 class d l- btl left negative output i(analog) none 48 class d r+ btl right positive output i(analog) none 43 class d r- btl right negative output i(analog) none 42 table 71. acs32201 tag analog output pins
idt confidential 54 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 8.3.4. acs32201 tag data and control pins to ta l p i n s : 1 0 8.3.5. acs32201 tag clock pins to ta l p i n s : 2 8 pin name pin function i/o internal pull-up pull-down pin location test a test pin do not connect i/o(digital) pull-down 16 test b test pin do not connect i/o(digital) pull-down 17 test c test pin do not connect o(digital) pull-down 18 dacbclk dac i 2 s shift clock i/o(digital) pull-down 13 daclrclk dac i 2 s framing clock i/o(digital) pull-down 14 dacdin dac i 2 s input data i(digital) pull-down 15 i2c_scl scl i 2 c shift clock i(digital) pull-up 19 i2c_sda sda i 2 c shift data i(digital) pull-up 20 spkr_en speaker enable i (digital) pull-up 52 test reserved test pin i(analog) pull-down 39 table 72. acs32201 tag data and control pins pin name pin function i/o internal pull-up pull-down pin location mclk master clock i(digital) none 34 nc no connect nc nc 6-9, 22-30, 33, 35, 53-55, 58-61, 63, 65-68 table 73. acs32201 tag clock pins
idt confidential 55 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 8.4. acs32201 na g pin tables 8.4.1. acs32201 nag power pins to ta l p i n s : 1 6 8.4.2. acs32201 nag reference pins to ta l p i n s : 1 8.4.3. acs32201 nag analog output pins to ta l p i n s : 4 pin name pin function i/o internal pull-up pull-down pin location pvdd btl supply i(power) none 12, 21 pvss btl supply i(power) none 16 dvdd_core dsp and other core logic+clocks i(power) none 30 dvddio interface (i 2 s, i 2 c, gpio) i(power) none 32 dvss digital return i(power) none 31 avdd analog core supply i(power) none 22, 25, 29 avss analog return i(power) none 23, 24, 27 vdd_pll1/3 pll supply i(power) none 6 vdd_xtal/pll2 pll supply i(power) none 9 vss_pll pll return i(power) none 7 vss_xtal oscillator return i(power) none 11 table 74. acs32201 nag power pins pin name pin function i/o internal pull-up pull-down pin location vref vref reference pin (bypass) i(analog) none 26 table 75. acs32201 nag reference pins pin name pin function i/o internal pull-up pull-down pin location class d l+ btl left positive output i(analog) none 18 class d l- btl left negative output i(analog) none 17 class d r+ btl right positive output i(analog) none 15 class d r- btl right negative output i(analog) none 14 table 76. acs32201 nag analog output pins
idt confidential 56 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 8.4.4. acs32201 nag data and control pins to ta l p i n s : 1 0 8.4.5. acs32201 nag clock pins to ta l p i n s : 4 pin name pin function i/o internal pull-up pull-down pin location dacbclk dac i 2 s shift clock i/o(digital) pull-down 33 daclrclk dac i 2 s framing clock i/o(digital) pull-down 34 dacdin dac i 2 s input data i(digital) pull-down 35 i2c_scl scl i 2 c shift clock i(digital) pull-up 5 i2c_sda sda i 2 c shift data i(digital) pull-up 4 spkr_en speaker enable i (digital) pull-up 20 test test a/b/c reserved test pin do not connect i(analog) none 13 36/2/3 table 77. acs32201 nag data and control pins pin name pin function i/o internal pull-up pull-down pin location mclk master clock i(xtal) none 8 nc no connect nc nc 10, 19/28 table 78. acs32201 nag clock pins
57 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 9. package information 9.1. package drawing note: to create a thermal pad size follow ?d2? and ?e2? value. ignore ?p? and ?k? figure 27. package outline 9.2. pb free process- package class ification reflow temperatures note: idt?s package thicknesses are <2.5mm and <350 mm 3 , so 260 applies in every case. package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6mm 260 + 0 o c* 260 + 0 o c* 260 + 0 o c* 1.6mm - 2.5mm 260 + 0 o c* 250 + 0 o c* 245 + 0 o c* > or = 2.5mm 250 + 0 o c* 245 + 0 o c* 245 + 0 o c* *tolerance: the device manufacturer/suppli er shall assure process compatibility up to and including the stated classification temperature (this means peak reflow temperature +0 o c. for example 260 o c+0 o c) at the rated msl level. table 79. reflow temperatures
58 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 10. nag/hla package information 10.1. nag/hla package drawing figure 28. nag/hla package outline 10.2. pb free process- package class ification reflow temperatures note: idt?s package thicknesses are <2.5mm and <350 mm 3 , so 260 applies in every case. package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6mm 260 + 0 o c* 260 + 0 o c* 260 + 0 o c* 1.6mm - 2.5mm 260 + 0 o c* 250 + 0 o c* 245 + 0 o c* > or = 2.5mm 250 + 0 o c* 245 + 0 o c* 245 + 0 o c* *tolerance: the device manufacturer/suppli er shall assure process compatibility up to and including the stated classification temperature (this means peak reflow temperature +0 o c. for example 260 o c+0 o c) at the rated msl level. table 80. reflow temperatures
idt confidential 59 v0.6 07/11 ?2011 integrated device technology, inc. acs32201 acs32201 low-power, high-fidelit y, class-d amplifier 11. ordering information yy = silicon revision, contact idt for current part number. 12. disclaimer while the information presented he rein has been checke d for both accuracy an d reliability, manufac- turer assumes no responsibility for ei ther its use or for th e infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal co mmercial applications. any other applications, such as those requiring extended temper ature range, high reliability, or other extraord inary environmental requirements, are not recommended without additi onal processing by manufacturer. manufacturer reserves the right to change any circuitry or spec ifications without notice. manufacturer does not authorize or warrant any product for use in life support devices or critic al medical instruments. ACS32201XTAGYYX tla package acs32201xnagyyx hla package
acs32201 low-power, high-fidelit y, class-d amplifier 6024 silver creek valley road san jose, california 95138 disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to mo dify the products and/or specif ications de- scribed herein at any time and at idt?s sole discretion. all in formation in this document, including descriptions of product fe atures and perfor- mance, is subject to change without notice. performance specifications and the operati ng parameters of the described products a re determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the information co ntained herein is provided without repres entation or warranty of any kind, whether express or implied, including, but not limited to, t he suitability of idt?s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the intellectual property r ights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other tra demarks and service marks used he rein, in- cluding protected names, logos and desi gns, are the property of idt or thei r respective third party owners. 13. document revision history revision date description of change 0.5 june 2011 initial release 0.6 july 2011 updated power consumption, tla package drawing.

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